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(Xilinx) OPB watchdog timer fails to release RESET

Hi, I'm working on a Microblaze system in a Spartan 3-2000. I am trying to implement a watchdog timer using the opb_timebase_wdt IP core. I'm currently using ISE/EDK 8.2.02i, and the WDT version is 1.00a.

The watchdog timer otherwise works fine. I can start/stop/reset the timer with no problem. The trouble is that when the watchdog timer DOES cause a reset, it won't release the reset line, which was effectively locking up the system. It did NOT respond like the datasheet.

To solve the immediate problem, I have inserted an edge detector into the reset control logic, which allows the system to reboot, but I can't get the WDT_Reset signal to go low at all. The end result is that the WDT can only reset the system once.

I did bring both signals out on test points, and I can see this behavior on a scope. The interrupt performs as expected, but once the WDT_Reset signal goes high, it stays high until I reconfigure the FPGA.

Note, I am using a custom reset controller, because the ComBlock 1200 board I'm using requires special treatment due to the clock situation. (the clock isn't stable until after configuration, causing DCM problems). Any reset input will cause both a sys_reset and dcm_reset. dcm_reset is released as soon as the reset input goes away, but sys_reset is held until the clock is stable for at least 64 clocks or so. I haven't had any other problems with this reset controller.

What am I missing here?

Thanks!

Reply to
radarman
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Why don't you copy C:\EDK81/hw/XilinxProcessorIPLib/pcores/ opb_timebase_wdt_v1_00_a to your local pcores directory and modify timebase_wdt_core.vhd to do what you want it to do?

Alan Nishioka

Reply to
Alan Nishioka

Ummm, the watchdog isn't clocked from the DCM, by any chance? I have seen a cunning synchronous reset block rendered completely inoperative by the fact that its own clock went away while it held the DCM in reset!

- Brian

Reply to
Brian Drummond

The source in /cygdrive/c/EDK81/hw/XilinxProcessorIPLib/pcores/ opb_timebase_wdt_v1_00_a/hdl/vhdl/timebase_wdt_core.vhd says that the state machine will only leave the ExpiredTwice state on OPB_Rst.

So you need an OPB_Rst to release the WDT_Reset line.

Alan Nishioka

Reply to
Alan Nishioka

After I inserted the edge detector, the OPB reset was being released. The trouble is that the watchdog timer refused to release ITS reset output, even after OPB Reset cycled..

The reset controller is operating from the input clock, not the DCM clock. It has to, in order to bring the dcm out of reset. The clock on this board is a bit difficult, because it's not free-running at configuration time.

Ultimately, the problem was solved another way. We have an async reset line going to another FPGA that can handle the problem. If the communications link goes down, the controller will just hit the "reset button"

Reply to
radarman

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