Hi All,
as I had guessed for long time the PMV primitive is actually the on-chip oscillator, most likely it is the same oscillator that is used for configuration. And it can be used from user designs as well. PMV is present in all recent FPGAs.
When I opened webcase about the issue that Xilinx tools made fatal failure when I tried to use the PMV from an hard macro the response was that, "you dont need to know" - well now I know :)
Antti
Ok, but when you create a schematic with a FPGA, which uses this undocumented feature and you produce some million parts, but Xilinx decide to cancel it in later revisions of the FPGA, you are lost.
-- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.de
Frank Buss schrieb:
sure - care should be taken when making any decisions. well currently it *IS* used by all Virtex-4 silicon, as the Xilinx tools use it for every design you make, you are just not seeing it. it is added silently, only visible in FPGA editor. so as long as the new Virtex-4 steppings are bitstream backward compatible the PMV feature will be there as well.
its just the configuration clock primitive - that is for some reasons made unaccessible (or not easily) accessible for the FPGA users.
Antti
Antti,
The PMV is not used for configuration.
In fact, it was not intended to be used by anything at all. It is there for test only.
As such, it is uncharacterized. Anything that is uncharacterized can NOT be made available for customer use. The DCM NBTI macro did make use of it, as that macro needed an oscillator for when no clock was present, and the less resource used by a macro, the better the macro (least impact on any design).
If you want a ring oscillator, (which is all that the PMV is), you can easily make one out of a chain of LUTs.
Aust> Hi All,
Austin Lesea schrieb:
Hi Austin,
hmm, well the PMV sounds like better oscillator than the chain of LUT's as it always in the same place and doesnt need LOC constraints etc? The PMV looks like a available replacement for the actual config clock primitive.
I still wish Xilinx FPGAs would have the config Clock accessible again as it was with old Xilinx FPGAs !
Antti
Antti,
As convenient as the PMV is, it is actually 16 different ring oscillators. We would have to fully characterize all of them in order to pick the "best" one, and then create a user macro to instantiate it...
Maybe some day, but right now it is not even on a list of "nice to have..."
Aust> Austin Lesea schrieb:
A little bit of a late response here, but the STARTUP_VIRTEX5 primitive gives you access to both the configuration clock and the internal housekeeping clock.
See
-m
Max Baker schrieb:
Thank You Max and Thanks to Xilinx
- I have been jammering about re-gaining the access to configuration clock for ages, now it has finally come true.
It was there in early Xilinx products, it is there in Altera and Lattice products, and since Virtex-5 it is again back in Xilinx products as well. Spartan3A doesnt seem to have it, but lets hope Spartan4 or upcomig Xilinx non-volatile products will have it in as standard feature.
Antti
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