xilinx: non LOC pins causing havoc

Howdy Matt,

First off, what do you mean by fail? Does PAR or MAP stop? Or does it make it through the tools and then somehow not work when you put it on the board?

I'm assuming you meant MAP or PAR would abort... in which case, I've had situations like that before. It seems like the tool isn't especially smart about how it assigns locations of things (especially GBUFs and DCMs) and walks itself into a corner it can't get out of. I seem to recall also having some problems with IOBs from time to time - it is as if the tools sometimes pick pins but ignore the banking rules. Then later, it detects the rule violation and stops. Again, this is from memory, so I may be remembering the situation incorrectly.

But since you have a board, you want all the pins nailed down, right?

Have fun,

Marc

Hi Mark, When I say fail, I mean the tool works fine and I d/l the design to my chip, but then after I run the design it fails in the lab after a few minutes. I know most of the logic is still functioning but some critical parts of it have stopped causing complete failure.

Matt

Howdy Matt,

I'm sure others in the group will come up with better ideas, but here's the first thoughts that ran through my mind when you say it fails after a few minutes:

1. Is it overheating?

1. Does it take about the same amount of time to fail every time you put power to it? If you change the inputs to the FPGA, does the amount of time change?

2. Are there any floating inputs on the device?

1. Any domain crossings that could lead to metastability (which could cause a partial lockup)?

Without knowing what it is that is locking up, these are about the only questions I know to ask.

Good luck,

Marc