Is there an easy way to get the Xilinx design manager to spit out a netlist for a synthesized VHDL file?
Adam
Is there an easy way to get the Xilinx design manager to spit out a netlist for a synthesized VHDL file?
Adam
Do you want an EDIF netlist? Xilinx tools generally create a .ngc file which can be converted using ngc2edif from the command line.
It depends on what kind of netlist you want. As mentioned earlier it is easy to get an EDIF netlist after the synthesis tool has run. But something which could also be useful is an XDL netlist which you can get after map or par has been executed.
(I guess I'm guilty of advocating XDL a lot lately but you can do some really nifty tricks with it if you don't care about portability that much :))
/Andreas
Ahem.. perhaps I should mention how to get such a netlist as well...
Use the xdl tool from the command line:
xdl -ncd2xdl yourdesign.ncd
/Andreas
What are some of the tricks you do with the xdl netlist? Does it give you a way to take a core through map and PAR and then use it as a block box in a design that is going to go through map/PAR again?
I have been wanting to harden some cores that I use in all my EDK designs, does this help any? I already have several cores that I pull in as black boxes and put area group constraints on. It would be nice to take those cores through PAR, and bring an already placed net list in as a block box.
Regards,
John McCaskill
One thing I've tried is to take a place and routed design and then insert another core that peeked on some internal signals in the first design. Think chipscope but using RS232 instead of JTAG for communicating with the outside world. The flow I used basically looks like this:
So it is not very streamlined I'm afraid :) But streamlining the process is really only a matter of writing a perl script. I haven't tried this on any large design either so I don't know if there are any gotchas...
Anyway, I would guess that there are quite a few possibilities here for someone with a lot of time on their hands.
Another use of XDL which is less radical is to extract information about the design. For a report I wrote some time ago I wrote an XDL to Postscript converter in order to avoid bitmap graphic of a floorplan :) And the xdlanalyze.pl script which I've mentioned on comp.arch.fpga earlier.
As you've probably guessed by now I'm afraid that my experimentation have not really been aimed at this... although I would be interested in knowing about such a solution as well.
/Andreas
I forgot to include an important part here:
/Andreas
Do you know if there is a way to get an xdl netlist back to an ngc netlist?
What I would like to do is to take some of my IO cores that I use on all of my designs and take them through PAR until I am happy with the results and then be able to use them as hard macros from then on.
Regards,
John McCaskill
Not that I know of. Well, you can use netgen to convert a .ncd design to vhdl or verilog and it might be possible to synthesize this one. However it would not contain routing information.
I've found conflicting information about routing in hard macros, some says the routing cannot be locked down like the following:
And some say that it is possible, such as a hard bus macro that is used in partial reconfiguration. Perhaps you could download such a bus macro and see how they are constructed?
Mind you, I haven't tried this at all so I have no idea if it is a good idea or not, but perhaps you could synthesize your I/O macros one after one and place the result in one large XDL file which you could then convert to NCD and use as a guide file for par. It is a quite ugly solution though, there must be a better way.
But if you find an easy way to create such hard macros I'd be interested as well :)
/Andreas
Sorry for the slow reply - winter colds stink ;) I was actually hoping to get a list of the synthesized logic equations prior to conversion to the Xilinx primitives. I was able to get an EDIF netlist but that's a bit too far down the tool chain as what I want to look at is the optimized Boolean logic. Is that possible? I seem to recall that generic vendor tools like Synplify had the ability to export such information prior to the selection of a target technology.
Adam
following:
I've never tried this, but to get the sum of products I guess you can tell the tools that you are synthesizing for a big PAL? I don't know how to get the SOP, factorized for the X architecture. But someone will step in if there's a way.
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