Xilinx Methodology Questions : Unconstrained Paths and DLL output phase alignment.

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Hi
  I have two questions regarding Xilinx designs.

[1] How do I identify which paths the static timing analyzer considers
to be unconstrained?  This has been an ongoing, frustrating task for me.
I am an extreme advocate of synchronous design, and to discover that
I have 97.3% constraint coverage is disconcerting.  That means 2.7% are
unconstrained.  Clearly the tool has identified these paths, and if there
was a way to display them, this would be helplful in isolating problem
areas.

[2]  Where does Xilinx post rules for treating the multiple clock outputs
of DLLs as synchronous?  From various postings to the newsgroup, I
get the impression that an clk0 and clk divide by 2, should not be treated
as synchronous, but either there is a small phase offset which precludes
the assumption of edge alignment, or the PAR/TRC tools can not handle
setup/holdtime from the two domains.  However, I have not read any
formal limitations placed on these outputs appearing in either data sheets
or  application notes.

--
Regards,
John Retta

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Re: Xilinx Methodology Questions : Unconstrained Paths and DLL output phase alignment.
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If you are using TRCE from the command line, it is the "-u xxx" option.
Also available in the GUI.

This adds a new section to the report (after all the normal timespec
sections), that lists unconstrained paths. You then play whack-a-mole
writing new time specs and re-running place/route/trce to make this
section of the report shorter and shorter, until hopefully you get it
to be empty.

Tragically you can get a situation where this section is empty, but
the coverage is still reported as not 100%. Xilinx waves its hands and
says that these are paths that can't/dont need to be constrained, such as
GND and VCC nets, and not to worry.   ... I do  ...

Sorry, I dont have an answer for your second question.

Philip



Philip Freidin
Fliptronics

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