So here's the scenario:
Virtex 2 6000 1152 board (dual Xeon 2.6 Win2k w/ 4GB RAM) Slice usage: 95% IOB,BRAM usage: 50% ISE 6.1 Mapper with -timing, -pr b, -k 8, -ol med as the only params: 39 hr until the mapper was done, then 1 hr in Par -ub -ol med All eight timing constraints were met.
ISE 5.2 with the same parameters: 1 hr in Mapper and 17 hr in Par All eight timing constraints were met.
So the 6.1 tools take twice as long to meet the same timing constraints. I recognize that on average the 6.1 tools have much better timing because of the timing in the mapper, and it's impressive that they ran for 40 hours without crashing, but is it worth the time cost? We've made great strides in Map/Par time, but 39 hours for one (non-reentrant) file on a fast machine? Is that average? In that the timing constraints aren't overly rigorous, what can I do to speed up the Map/Par time? How come no one has written these tools to run in the Xilinx hardware? Or with some kind of accelerator board? Thanks for your time.