-- The code
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM; use UNISIM.VComponents.all;
entity top is port( sys_clk_in : in std_logic; sys_rst_in : in std_logic; data_in : in std_logic_vector(3 downto 0); dq : inout std_logic; q1 : out std_logic; q2 : out std_logic; q3 : out std_logic; q4 : out std_logic; q5 : out std_logic; q6 : out std_logic ); end top;
architecture Behavioral of top is
component sys_dcm port( clkin_in : in std_logic; rst_in : in std_logic; clkin_ibufg_out : out std_logic; clk0_out : out std_logic; clk2x_out : out std_logic; clk2x180_out : out std_logic; clk90_out : out std_logic; clk180_out : out std_logic; clk270_out : out std_logic; locked_out : out std_logic ); end component;
signal sys_clk : std_logic; signal sys_clk180 : std_logic; signal sys_clkdiv : std_logic; signal sys_clkdiv90 : std_logic; signal sys_clkdiv180 : std_logic; signal sys_clkdiv270 : std_logic; signal sys_lock : std_logic; signal sys_lock_delayed : std_logic; signal sys_rst_in_not : std_logic; signal sys_reset : std_logic;
signal iobuf_i : std_logic; -- data read signal iobuf_t : std_logic; -- data write enable signal iobuf_o : std_logic; -- data write
signal idelay_rdy : std_logic;
begin
sys_rst_in_not sys_clk_in, rst_in => sys_rst_in_not, clkin_ibufg_out => open, clk0_out => sys_clkdiv, -- 100 MHz clk2x_out => sys_clk, -- 200 MHz clk2x180_out => sys_clk180, -- 200 MHz clk90_out => sys_clkdiv90, -- 100 MHz clk180_out => sys_clkdiv180, -- 100 MHz clk270_out => sys_clkdiv270, -- 100 MHz locked_out => sys_lock );
sys_lock_delay_SRL16 : SRL16 generic map ( INIT => X"0000") port map ( Q => sys_lock_delayed, A0 => '1', -- 16 clock delays A1 => '1', A2 => '1', A3 => '1', CLK => sys_clk, D => sys_lock );
sys_reset idelay_rdy, -- 1-bit output indicates validity of the REFCLK REFCLK => sys_clk, -- 1-bit reference clock input RST => sys_reset -- 1-bit reset input );
iserdes_inst : ISERDES generic map ( BITSLIP_ENABLE => FALSE, -- TRUE FALSE DATA_RATE => "DDR", -- DDR SDR DATA_WIDTH => 4, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7,8 INIT_Q1 => '0', INIT_Q2 => '0', INIT_Q3 => '0', INIT_Q4 => '0', INTERFACE_TYPE => "MEMORY", -- model - "MEMORY" or "NETWORKING" IOBDELAY => "IFD", -- delay chain "NONE","IBUF","IFD","BOTH" IOBDELAY_TYPE => "FIXED", -- tap delay "DEFAULT", "FIXED","VARIABLE" IOBDELAY_VALUE => 1, -- initial tap delay 0 to 63 NUM_CE => 1, -- clock enables 1,2 SERDES_MODE => "MASTER", -- "MASTER" or "SLAVE" SRVAL_Q1 => '0', SRVAL_Q2 => '0', SRVAL_Q3 => '0', SRVAL_Q4 => '0') port map ( O => open, Q1 => q1, Q2 => q2, Q3 => q3, Q4 => q4, Q5 => q5, Q6 => q6, SHIFTOUT1 => open, SHIFTOUT2 => open, BITSLIP => '0', CE1 => '1', CE2 => '1', CLK => sys_clk, CLKDIV => sys_clkdiv90, D => iobuf_o, DLYCE => '0', DLYINC => '0', DLYRST => '0', OCLK => sys_clk, REV => '0', SHIFTIN1 => '0', SHIFTIN2 => '0', SR => sys_reset );
oserdes_inst : OSERDES generic map ( DATA_RATE_OQ => "DDR", -- Specify data rate to "DDR" or "SDR" DATA_RATE_TQ => "DDR", -- Specify data rate to "DDR", "SDR", or "BUF" DATA_WIDTH => 4, -- DDR 4,6,8,10 SDR 2,3,4,5,6,7, or 8 INIT_OQ => '0', -- INIT for Q1 register INIT_TQ => '0', -- INIT for Q2 register SERDES_MODE => "MASTER", -- Set SERDES mode to "MASTER" or "SLAVE" SRVAL_OQ => '0', -- Define Q1 output value upon SR assertion SRVAL_TQ => '0', -- Define Q2 output value upon SR assertion TRISTATE_WIDTH => 4 ) -- Specify parallel to serial converter width ?? port map ( OQ => iobuf_i, -- 1-bit output SHIFTOUT1 => open, -- 1-bit output SHIFTOUT2 => open, -- 1-bit output TQ => iobuf_t, -- 1-bit output CLK => sys_clk, -- 1-bit input CLKDIV => sys_clkdiv, -- 1-bit input D1 => data_in(0), -- 1-bit input D2 => data_in(1), -- 1-bit input D3 => data_in(2), -- 1-bit input D4 => data_in(3), -- 1-bit input D5 => '0', -- 1-bit input D6 => '0', -- 1-bit input OCE => '1', -- 1-bit input REV => '0', -- 1-bit input SHIFTIN1 => '0', -- 1-bit input SHIFTIN2 => '0', -- 1-bit input SR => sys_reset, -- 1-bit input T1 => '0', -- 1-bit input T2 => '0', -- 1-bit input T3 => '0', -- 1-bit input T4 => '0', -- 1-bit input TCE => '1' -- 1-bit input );
iobuf_inst : IOBUF port map ( I => iobuf_i, -- data going out of FPGA T => iobuf_t, -- data write enable O => iobuf_o, -- data coming into FPGA IO => dq -- dq inout port );
end Behavioral;