hello all, I just downloaded Xilinx ISE8.1 and Memory Interface Generator MIG1.5. I selected a DDR2-Sodimm to implement in a Virtex4. MIG1.5 generates a complete synthesizable testbench and the batch file "ise_flow.bat" When I start the batch file all works fine till xilinx map tool stops with an internal error: FATAL_ERROR:Map:Portability/export/Port_Main.h:127:1.24. Is there anybody with same problem on MIG1.5 thanks for help peter
there is on very sad thing, namly as soon as you get
... Portability ... 127
error means that you need to wait for next service pack or quickpatch.
its generic error and doesnt give any hint what is actually wrong. like a generic root of all devil by xilinx software.
the same main.h:127 just keeps coming, in each major release, in each service pack :(
Antti PS if you need to quick test DDR2 then EDK 8.1 SP1 has DDR2 and that does pass synthesis at least, no crash, havent tested the hardware if it works also though.
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.