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Xilinx ISE tutorial revisited using MyHDL

Hi all:

I have added a page to the MyHDL Cookbook, about a stopwatch design similar to the design from the Xilinx ISE tutorial:

formatting link

The design is tackled in "the MyHDL way". The page describes the whole flow, including unit testing, automatic conversion to Verilog, and FPGA synthesis results.

MyHDL is a Python package that turns Python into a HDL.

Best regards,

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com
Reply to
Jan Decaluwe
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Hi all:

I have added a page to the MyHDL Cookbook, about a stopwatch design similar to the design from the Xilinx ISE tutorial:

formatting link

The design is tackled in "the MyHDL way". The page describes the whole flow, including unit testing, automatic conversion to Verilog, and FPGA synthesis results.

MyHDL is a Python package that turns Python into a HDL.

Best regards,

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com
Reply to
Jan Decaluwe

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