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Xilinx ISE Passing IO pad attributes using UCF file.

Hi, I am using a ucf file to pass pin location, iostandard, slew rate and drive strength constraints to the xilinx PAR tools. ISE 7.1 SP4, the part I am targetting is XC3S50-4TQ144C.

I use the following statement in my UCF file. INST "potsSdo" LOC = P79 | IOSTANDARD=LVCMOS33 | SLEW=SLOW | DRIVE=8;

At the Translate stage of the tools a warning(as below) is issued telling me that my attribute/contraint is being ignored. (I have 96 other statements in the UCF very similar to the one above, so I am puzzled that the tools should only complain about this one).

WARNING:NgdBuild:486 - Attribute "IOSTANDARD" is not allowed on symbol "potsSdo" of type "FD". This attribute will be ignored. WARNING:NgdBuild:486 - Attribute "SLEW" is not allowed on symbol "potsSdo" of type "FD". This attribute will be ignored. WARNING:NgdBuild:486 - Attribute "DRIVE" is not allowed on symbol "potsSdo" of type "FD". This attribute will be ignored.

It would seem from the warning that the tools are trying to apply the constraint to an "FD" element which I suspect is a D flip flop. Of course I want the tools to be applying the constraint to the IO PAD rather than any logic elements inside the design. There were no warnings issued for the other 96 similar constraints I have in the ucf file. Any ideas on where to look to figure out why the tools not applying this constraint to the IO Pad?

I guess I could instantiate the IO pad directly, but why do I need to. I'm worried there is something more sinister going on here that will bite when I come to test...

(I have read the Xilinx constraints guide.)

Any ideas, hints etc much appreciated.

Regards Andrew

Reply to
Andrew FPGA
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I use something like:

NET "net_name" LOC = "AB26" | IOSTANDARD = LVCMOS25 | PULLDOWN ;

where net_name is the name of the I/O signal.

Although I don't use it to create my UCF files, I sometimes employ the Xilinx constraints editor to determine correct syntax. (Maybe things have changed, but the last time I tried to use it for design, the constraints editor generated UCF files that were far too messy and verbose for my tastes.)

Bob Perlman Cambrian Design Works

Reply to
Bob Perlman

Hi Bob, Thanks, yep replacing my INST with NET fixes my problem.

Regards Andrew

Bob Perlman wrote:

Reply to
Andrew FPGA

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