Hi All, I was wondering is there any way to synthesis a design of mine on an FPGA using the ISE tool so that I can get results for area speed, xpower and such. It is a partial prooduct summation tree that adds 13
12-bit numbers in a weighted manner. The tool tries to assign its input and output ports to pins and i get a worning to say that more than 100% of the device is used up even though it only uses 8% of the gates. I was wondering is there a way to unbond the ports from the pins. I was thinking just box it up and buffer it but not sure.Thanks Keith