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XILINX ISE: How to define a Internal clock and use it in OFFSET command?

Hi,

I have a input clock "i_clk_main", in my VHDL code, i divide this clk with factor 2, that means "clk_int" has the half frequenz as "i_clk_main", and i use "clk_int" to clock the output register.

Now, i must in the constraint file define, how much ns delays the output relative to "clk_int" may maximal have. What should i do? The following is the error report fomr ISE.

Checking timing specifications ... ERROR:XdmHelpers:634 - Signal "clk_int" is used as the clock in specification "OFFSET=OUT 7000 pS AFTER clk_int HIGH", but this clock signal is not connected directly to a pad. An OFFSET specification must use a pad signal to designate the clock.

Thanks, and have a nice weekend Cheng

Reply to
uvbaz
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Instead of tying using clk_int as a clock, you might try using it as an enable for your synchronous devices, and clock them using i_ckk_main. Then the tool can calculate your OFFSETs. One hazard with this approach is that if you are already using the CE pins, this will add more logic to the CE paths. With this approach, you also have to use multi-cycle timing contraints. This can be done by creating a group with clk_int: NET "clk_int" TNM_NET = "slow_devs"; and then TIMESPEC "TS_slow_devs" = FROM "slow_devs" to "slow_devs" = main_period*2; The hazard here is that your synthesis tool may replicate clk_int, and you have to chase all copies of it to include all half-speed devices in the slow_devs group.

Once the above is done, you can make all your OFFSETs relative to i_clk_main.

HTH Just John

Reply to
JustJohn

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