Hi,
ISE reports an out of memory error while synthesizing a design which has 10,000 instantiations of a simple verilog module. The module uses Xilinx primitives FDRSE, RAM32X1S and few assign statements and no other type of statement.There are broadcast connections to all above modules from a central controller and some outputs of each module are connected as inputs to the next module in a daisychain manner.
When I instantiate this module 1000 times the tool is able to synthesise and implement the design. But for 10,000 instantiations, the Xilinx ISE tool reports an out of memory error during synthesis.
I'm using Xilinx ISE evaluation version 9.2i. Target device is Virtex-5 XC5VLX330 and it has plenty of space to accomodate the 10,000 instantiations. The system on which the tool is running has 2GB of memory.
Any help in this regard would be greatly appreciated.
Thanks in advance Ashwini