Xilinx ise 9.2i clean up project files

Just recently an error/bug arises in ISE when i go to synthesise a design. The synthesis will just error without any transcript text. when i cleanup the project files and then run XST it synthesises perfectly.

Anyone have the same problem/ found a fix?

Reply to
mozilla
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I think you just mentioned the fix: cleanup the project.

This problem usually occurs if you add/change/delete modules from the hierarchy. I've also heard of this happening more frequently with EDK, but I don't use EDK myself. Are you saying you need to cleanup the project each time you want to rebuild (i.e. no new modules just some editing of existing modules)? I haven't seen that happen.

The other workaround I found was to just start a new project and include all of my sources from the broken one. That is a real pain, though.

Good Luck, Gabor

Reply to
Gabor

Yes, I'm seeing the same thing on some projects but not all. My problem is that when I go back and forth between simulation and Xilinx PPR it forces me to cleanup project files before it will run. In other words, if just ran PPR and now I want to simulate it won't, without cleanup. If I have just simuleted, I can't run PPR without cleanup. Its a pain. Anyone got a fix? A rebuild works, but its very painful, and I'm not sure it will work every time.

Dan

Reply to
Dan K

When I was experimenting I found ISE would eat my project or hang eating all the CPU if I wasn't very careful (with 8.2) and I also wanted to swap between architectures. Furthermore the .ise file is not suitable for version control... I did some research and found there is a tool you can use to recreate the ISE file from a plain text file (you lose some info but it is very usable)

Create the file foo.npl with the following contents.. # Create the project NewProject(foo.ise)

# Set basic properties SetProperty(Device Family, spartan3) SetProperty(Device, xc3s400) SetProperty(Package, tq144) SetProperty(Speed Grade, -4) SetProperty(Top-Level Module Type, HDL)

# Add the sources AddSource(foo.v, Verilog Design File) AddSource(foo.ucf, SA) AddSource(abc.xco, Coregen Design File)

# Test bench sources AddSource(foo_test.v, Verilog Design File)

# This doesn't actually work.. SetProperty(Simulation Run Time, 5000 ns, foo_test_v, Simulate Post-Place & Route Model, 9, SA)

# Close the project to tidy up CloseProject()

Then run pjcli -f foo.npl

I've tested this on FreeBSD (linux emulation) & Windows with ISE8.2.

Hope it helps.

--
Daniel O'Connor software and network engineer
for Genesis Software - http://www.gsoft.com.au
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Reply to
Daniel O'Connor

Route Model, 9, SA)

If you have an older version of ISE (6.x works) you can generate the .npl file from the GUI. One thing I found out about ISE 8.x and later is that if you "upgrade" a project from 6.x to 8.x, your .npl file gets trashed in the process (I guess they really don't want you keeping a project setup in clear text). So it's a good idea to back up the .npl file first.

Reply to
Gabor

How about if cleaning up project files does not help?

I would like to avoid recreating the project due to the size of the schematic to be redrawn. I have the same symptoms as mentioned in the first post, except cleaning project files does not solve the problem. However, when opening the ".ucf" file for my project, Xilinx ISE goes through a "synthesis" before that file can be opened. This backdoor synthesis runs fine, but not by activating the synthesize, implement, or generate prog. file options...

Any thoughts?

Reply to
Tim P

I've tried running pjcli -f xxxx.npl as you mentioned but the problem still remains. The problem seems to be when i swap between behavioural and synthesis/implementation.

I think it may be webcase time.

Reply to
mozilla

in fact i was wrong it does seem to fix the problem thank you....

Reply to
mozilla

I wouldn't think you need to re-draw any schematics, just include the existing ones in the new project. It isn't your source files that are messed up (usually), but the project itself (.ise file). Regards, Gabor

Reply to
Gabor

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