Hi,
I am working on an DSP, have problem by data receiving. As listed below, xilinx ise tools build a "DELAYCHAIN" into the circuit, as a result, the data needs 7.956ns from PADS to FlipFlops. My questions are:
- How can i control the tools, to build or not to build the "DELAYCHAIN".
- When the data need 7.956ns, to get to the FFs, will it works, when the datarate 150MHz (6.6ns) is?
Timing report from XILINX ISE 9.1i ====================================================== Delay type Delay(ns) Logical Resource Tiopi 0.943 i_data i_data_2_IBUF net (fanout=1) 0.063 i_data_2_IBUF Tidockd 6.950 instance1/data_int.DELAYCHAIN instance1/data_int_2 Total 7.956ns (7.893ns logic, 0.063ns route) (99.2% logic, 0.8% route) =======================================================
Thanks Cheng