So, Austin and the other Xilinx people that monitor the board-- Why is Xilinx not willing to take the hour to fix a show stopper problem that has existed for at least a year in at least NINE versions of ISE?
There have been 7 sevice packs issued which still have this problem. This means it is a management decision to not fix things. The fact that the service pack and the release came at the same time was a very bad sign.
On the other hand, could I get a job as a xilinx programmer, or better yet, as a manager. I have always had bosses who exptected me to do things correctly. This would be a nice change.
Hi, I wrote some Makefiles that we use in a course here. The entire lab skeleton is actually available for download but I have uploaded just the Makefiles to my homepage if you are interested:
formatting link
It is not perfect but it works ok for me and most students in the course seem to think so as well :) They have been tested in both Linux and cygwin.
I wrote the Makefiles for the following reasons:
Since they are text based, revision control is easy
We can avoid the (for now) unstable Project Navigator
Building a project will not spew lots of temporary files in the project directory. (They will end up in the synthdir directory.)
The Makefile has been tested with ISE 8.1 and 8.2.
I also have a small shell script which I use to build small projects where I haven't bothered to create a Makefile. That is also available on the web page. It is heavily inspired by the Makefile mentioned above.
Some things which would be nice to be able to handle:
VHDL libraries (not everything should end up in work)
Don't recompile all files when starting a simulation target
Mixed VHDL/Verilog in the Makefiles
Tips and tricks for these Makefiles will be gratefully received :) I know that they are a bit ugly at the moment.
Interesting - could you say any more about what makes vhdl-mode so bad? My experience has been more of people thinking Emacs sucks, but they wish their editor did all that vhdl-mode does!
Thanks, Martin
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
Sure that's VHDL mode? I can't see anything in the docs about simulation..
Hmm, it looks very interesting but I use Verilog :)
I need to know the commands.. I am software guy and all the "compile" steps are confusing :)
--
Daniel O'Connor software and network engineer
for Genesis Software - http://www.gsoft.com.au
"The nice thing about standards is that there
are so many of them to choose from."
-- Andrew Tanenbaum
GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C
Completion/templates get in the way of my typing. I know what I want to write, but if the editor starts inserting stuff for me, I have to think about the typing much more, so it slows me way down.
--
Daniel O'Connor software and network engineer
for Genesis Software - http://www.gsoft.com.au
"The nice thing about standards is that there
are so many of them to choose from."
-- Andrew Tanenbaum
GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C
Ahh, yes I can understand that - I had a similar problem except that when I started, I was very rusty at VHDL, so it helped. I'm now so used to the templates that inserting a new process becomes: procthen type in s docunmmentation comment if I feel like it and prod enter a few times to get rid of any extraneous prompts.
That sounds like a right palaver, but honest, it helps me :-)
I wrote a new piece of code the other day and it compiled first time, because the templates and tab-completion of variables/signals meant my customarily inaccurate typing hadn't caused any syntactical problems.
Cheers, Martin
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here.
All logos and trade names are the property of their respective owners.