Xilinx ISE 8.2.3 - Re-Creating Projects

Hi

A couple of months ago I had to move up to ISE 8.2 once 7.1 stopped meeting my timings. Since I moved I have had nothing but problems with project files and their corruption. I have finally settled on 8.2.3 as it appeared more stable than older patched versions. 8.2.0 was dire.

The project file corruptions seem to occur randomly and will do various things, such as remove all files from the project (and not let you add them back), or not let you edit coregen parts, or a host of other things.

Re-creating a project each time seems very laborious. Does anyone have any shortcuts to do this? Is there a TCL script that can be run? Archiving and Project Cleanup don't help.

The project is a mix of VHDL, verilog and coregen parts (xaw and xco).

Why can't they just implement project files as text files and let you control them by hand?

Regards Marc

Hi

A couple of months ago I had to move up to ISE 8.2 once 7.1 stopped meeting my timings. Since I moved I have had nothing but problems with project files and their corruption. I have finally settled on 8.2.3 as it appeared more stable than older patched versions. 8.2.0 was dire.

The project file corruptions seem to occur randomly and will do various things, such as remove all files from the project (and not let you add them back), or not let you edit coregen parts, or a host of other things.

Re-creating a project each time seems very laborious. Does anyone have any shortcuts to do this? Is there a TCL script that can be run? Archiving and Project Cleanup don't help.

The project is a mix of VHDL, verilog and coregen parts (xaw and xco).

Why can't they just implement project files as text files and let you control them by hand?

Regards Marc

Did you post this three times by intention :-) ?

Well I also had problems with projects. The only thing to do: Snap Shots and manual archives with Winrar.

Isn't it great? I find the Xilinx simulator will hang too!

You can use pjcli (which is a [gross] Tcl script) like so.. pjcli -f ./npl_cmdfile

cat ./npl_cmdfile # # Script file for pjcli to [re]create the .ise file # # $Id$ #

# Create the project NewProject(project.ise)

# Set basic properties SetProperty(Device Family, spartan3) SetProperty(Device, xc3s400) SetProperty(Package, fg456) SetProperty(Speed Grade, -4) SetProperty(Top-Level Module Type, HDL)

# Add the sources AddSource(foo.v, Verilog Design File) AddSource(foo.ucf, foo) AddSource(bar.xco, Coregen Design File)

# Test bench sources AddSource(foo_test.v, Verilog Design File)

# Seems to affect all files..? SetProperty(Simulation Run Time, 5000 ns, foo_test_v, Simulate Post-Place & Route Model, 9, foo)

# Close the project to tidy up CloseProject()