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Xilinx ISE 6.1 Clocking Wizard - no hdl generated?

Hello,

I'm using dcm's in a V2 design and I noticed that there is a Clocking Wizard in the new 6.1 tools. It looks useful because it allows you to go through the options to generate a correctly generic'ed and attributed dcm instantiation. The online documentation says that it will generate an hdl module that can be inserted into a design but I get no hdl when I run the wizard.

Is there a trick to get hdl from the Clocking Wizard?

Regards

Reply to
Pete Dudley
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I see now how to do it. When the Clocking Wizard source is selected within the Project Navigator there are process options to View HDL and View HDL Instantiation Template.

Wizard

Reply to
Pete Dudley

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