Hello All:
Jsut an update on my efforts on using the Xilinx IPIF for a PLB master.
Per another user's recommendation (thanks Alan Nishioka), I looked at the PLB spec from IBM and wrote my own interface.
After several days of messing with the Xilinx IPIF fucntions, I could not get the master functionality to work correctly.
I did, however, get my own to work pretty much on the first try.
I wrote a simple peripheral that updated the contents of DDR memory every second with an increasing value (address zero got a 0; address 1 got a 1, etc.)
Moral of the story: Read the PLB datasheet and you will be able to make whatever you want very quickly. It took me a total of 8 hours of reading through the datasheet and coding up my own state machine.
If anyone wants to see my code (in Verilog), let me know.
Thanks for all the help.
-Eli