Xilinx IPIF PLB Master Update

Hello All:

Jsut an update on my efforts on using the Xilinx IPIF for a PLB master.

Per another user's recommendation (thanks Alan Nishioka), I looked at the PLB spec from IBM and wrote my own interface.

After several days of messing with the Xilinx IPIF fucntions, I could not get the master functionality to work correctly.

I did, however, get my own to work pretty much on the first try.

I wrote a simple peripheral that updated the contents of DDR memory every second with an increasing value (address zero got a 0; address 1 got a 1, etc.)

Moral of the story: Read the PLB datasheet and you will be able to make whatever you want very quickly. It took me a total of 8 hours of reading through the datasheet and coding up my own state machine.

If anyone wants to see my code (in Verilog), let me know.

Thanks for all the help.

-Eli

Reply to
Eli Hughes
Loading thread data ...

Yes, I'd like to. To get my real email, just do a 'endian swap' on my email ;) I was just about to start using the IPIF for PLB master but if I can interface to the PLB myself and save some slices (the IPIF is 1000 slices with DMA!)

thanks,

Sylvain

Reply to
Sylvain Munaut

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.