XILINX IPCore

Hello,

I recently bought a board that has a firewire port that uses PCI32 as a communication to the TI Link layer chip. I was told that I could easily communicate with the board by FPGA using Xilinx IPcore. I followed the steps on "Getting Started User Guide" i.e. inserting the device id, vendor id values and etc, getting the .ngc file and then get the .bit file and used iMPACT. However, after several attempts, my linux machine still could not detect the board.

Does anyone has any suggestion on this?

Cheers!

Reply to
Ace
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A few more details like the board being used would be useful but here is s a few things to check.

If you are using the PCI core as a Host Bridge and your end is the main master in the system then you need to configure any PCI based cards or chips on that PCI bus using configuration cycles.

If you are a plug in card check presence lines are implemented.

Worth checking if you are a Target that would not getting hung or aborted cycles. Whole bunch of reasons for these. PCI implementations in PCs are generally not very good at handling errors, like no response, and generally hang if anything is mildly wrong.

Check your pinout is correct.

John Adair Enterpoint Ltd.

Reply to
John Adair

Is your board fully programmed and responsive to PCI cycles before the PC BIOS starts looking at the PCI bus? If it doesn't assert DEVSEL for the first config read cycle, a modern motherboard will probably take away its clock and never speak to it again. Even looking later from an OS you will not see it since it will not have a clock.

--
Ben Jackson AD7GD

http://www.ben.com/
Reply to
Ben Jackson

It has been many years since I used the Xilinx PCI core, but...

There was a short errata sheet that required VERY careful reading to make the core work.

Two of the things I remember were the reset pin being in the wrong place and one clock being run through a BUF rather than a BUFG.

And you do know that the FPGA -must- be initialized before the ROM BIOS does the power-on bus scan, right?

HTH

Reply to
ghelbig

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