Xilinx IP: PCI Express

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Hi, we recently bought the PCI Express Endpoint Core from Xilinx and implemented
it into a Virtex 2 Pro 50 device.

We have some experience with MGT connections and never had problems.

But up to now we could not get the core running. We expect that the core will be
detected by the BIOS of our PCI Express PC - but nothing happened.

We could measure a stable reset pulse at boot-up of the PC. We expect that the
signal trn_lnk_up_n will go high during link training and then goes low to
indicate link up. But this signal stays low all the time.

BTW: We heard that the Spread-Spectrum feature of some mainboards is critical,
but as far we can measure there is no modulation of the 100MHz mainboard
provided clock.

Does anybody here have any experience with the usage of PCIexpress in FPGA ? Any
suggestions welcome !

Regards Andreas

Re: Xilinx IP: PCI Express
Quoted text here. Click to load it
implemented it into a Virtex 2 Pro 50 device.
Quoted text here. Click to load it
will be detected by the BIOS of our PCI Express PC - but nothing happened.
Quoted text here. Click to load it
the signal trn_lnk_up_n will go high during link training and then goes low
to indicate link up. But this signal stays low all the time.
Quoted text here. Click to load it
critical, but as far we can measure there is no modulation of the 100MHz
mainboard provided clock.
Quoted text here. Click to load it
? Any suggestions welcome !
Quoted text here. Click to load it

both nital and dinigroup have working xilinx PCIe FPGA boards. try dini
first see if they would be willing to help.

Antti



Re: Xilinx IP: PCI Express
Hello,

If you haven't done so already, please file a support case with the Xilinx
hotline.  Make sure to specify what version of the IP core you are using,
and it would probably help if you also submitted a schematic of your board.

Eric Crabill

Quoted text here. Click to load it
implemented it into a Virtex 2 Pro 50 device.
Quoted text here. Click to load it
will be detected by the BIOS of our PCI Express PC - but nothing happened.
Quoted text here. Click to load it
the signal trn_lnk_up_n will go high during link training and then goes low
to indicate link up. But this signal stays low all the time.
Quoted text here. Click to load it
critical, but as far we can measure there is no modulation of the 100MHz
mainboard provided clock.
Quoted text here. Click to load it
? Any suggestions welcome !
Quoted text here. Click to load it



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