Xilinx IOSTANDARD for PCI-X 100MHz interface

If you are using Xilinx PCI-X LogiCORE, all the constraints are defined in core's UCF file and the wrapper files instantiate PCIX buffers. So you don't need to add any IOSTANDARD constraint in UCF file.

PCIX IO buffers are listed in docs @

-Vikram

Nahum Barnea wrote:

I'm looking at table 2-62 on p.331 of my 2VP databook that lists PCI33_3, PCI66_3, and PCIX I/O specs. Maybe you were searching for PCI-X instead of PCIX.

Nahum Barnea wrote:

You are right, I am searching for PCI-X (i.e NOT PCI express).

PCIX.

If you look in the *_lc*x files that come with the Xilinx PCIX core, you will see they already use the PCIX standard for primitive names, i.e., IBUF_PCIX, etc. If you're planning to write your own PCIX core, don't bother. Just spend the $15k (talk them down from $18k.) That would be the equivelant of two months for two good developers. I know some developers that could do it that fast, but none of those will work for that cheap.

That statement really concerned me: PCIX doesn't have anything to do with PCI Express.

PCI33_3,

of PCIX.

frequency.

Hi,

Some additional information that may help:

Virtex-E has a PCIX66_3 SelectIO mode, which is useful for PCI-X implementations at 66 MHz. It is not meant for use at 133 MHz.

Virtex2 and Virtex2Pro have a PCIX SelectIO mode, which is useful for both 66 MHz PCI-X and 133 MHz PCI-X.

Whichever you use, keep in mind all the I/O has to be registered in the IOBs. You will also need to use a DLL/DCM.

We have done it this way. I am told that the "way of the future" is to just use IBUFs, etc... and use IO standard constraints in the UCF. Both work.

Thanks for the plug for our PCI and PCI-X cores. I also believe if you buy this kind of IP from a reputable vendor (of which there are more than one) at sub-$20K pricing, you are saving yourself a lot of time and money.

Eric