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Xilinx IOB flop mapping vs. -bp switch

A question for the Xilinx guru's out there:

I am experimenting with the map -bp switch (map slice logic) in order to make better use of device resources.

I am constraining my outputs with IOB = TRUE so that the mapper maps them to IOB flops. When I use the -bp switch, however, I have an output flop that is mapped to a block RAM despite the IOB constraint. The clk-to-out timing specification is unreachable so the map fails with an error message. I have tried applying the IOB constraint in the verilog and in the UCF file.

Is there a way to force the mapper to ignore the -bp switch for certain flops (other than creating and maintaining a mapping file), or am I stuck with having to choose between IOB packed flops and block RAM mapping?

I am using ISE6.1i.

Thanks in advance!

Mark

Reply to
schellho
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Hi Mark,

Try assigning the same BLKNM attribute to the FF and Pad, or a LOC constraint on the FF if you already have an IO layout. These are both harder constraints than IOB = TRUE and should work.

Another approach would be to specify the logic to be packed into BRAM using the file based system documented in Answer Record 15888.

Regards, Bret

Reply to
Bret Wade

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