hi,
im having trouble infering a dual port ROM with xilinx ISE 5.2i. I can infer dual port RAM, but i need it to be ROM in order to have it initialised. does anybody know how to do it? i've been searching the web and xilinx website, but i havent seen how to infer a dual port ROM, only regular ROM, but i need to do two read access (and given that the ROMs will be implemented in BlockRAM, it'd be a waste if i had to use two cycles to read from dual port capable BlockRAMs) i'd like the approach to be VHDL, cause it seems that you can do it with Coregen?? but i want it to be VHDL cause the ROM generation has to automatic (thru a C program that generates VHDL code) comments are welcome, TIA