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Xilinx iMPACT error: "Done did not go high"

I have a Virtex xc2vp20 FPGA mounted on a Xilinx HW-AFX-FF1152 board. The FPGA is in a JTAG chain with two ROM modules, although I am not using the ROM modules right now.

I am trying to learn how to use the embedded PowerPC module on the FPGA, and for this purpose, trying to implement the example design that Xilinx gives with their EDK tutorial. After I carry out all the implementation steps (with some small modifications to account for my board) and generate a bitstream, I am not able to download it onto the FPGA using iMPACT. iMPACT reports "Programming stopped: Done did not go high". The "DONE" LED on the board does light up, however, but the application does nothing (of course, I have no way of knowing if the application is correctly implemented at this stage). Also, the board's "Program" button becomes completely unresponsive after the failed configuration and I have to power-cycle the board to use it again.

Here is the setup I have:

  1. HW-AFX-FF1152 board, Virtex2Pro xc2vp20 FPGA
  2. Xilinx ISE 6.1.03i
  3. Xilinx EDK 6.1.2
  4. Windows XP on the host machine
  5. Configuration with JTAG using the Parallel Cable IV

I have done all the sanity checks I could think of, and also looked through whatever the web had to offer but that has not fixed my problem. Does anyone have any ideas why I may be seeing this?

Thanks, Mahim

PS: I have been asking for a lot of help lately. I am more-or-less a complete newbie to hardware, and in a situation where I have to learn a lot really fast :(

Reply to
Mahim Mishra
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Try changing the mode of your parallel port from the BIOS. If forget which one works, I think it's ECP.

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Martin Euredjian

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Reply to
Martin Euredjian

I am able to configure a design onto the FPGA if it does not use the PowerPC core, using the same tools and setup. I see this failure only if I try to use the PowerPC core in my design.

I also checked the bitgen.ut that Xilinx ISE/Platform Studio produces for my design and it matches exactly the bitgen.ut that ISE generates for a project that does not use PowerPC and which I am able to download successfully, so it is also (probably) not some pin being pulled up or down wrong.

Thanks, Mahim

Reply to
Mahim Mishra

Hi Mahim,

as you're only using on of the PPCs you might also want to try instantiate the secod one as a dummy-PPC. Just copy it in the MHS-file. Maybe it helps....

Cheers,

Mart>

Reply to
Martin Kellermann

It's nice to see comp.arch.fpga getting back to its roots. ;-)

--Mike

Reply to
Mike Butts

Hi I had the same problem. All you have to do is use pullup for TRSTNEG and HALTNEG pins using PACE. Ram

Reply to
ram

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