XILINX : IBIS model creation

Hi, I am using xilinx ISE 8.1 webpack version.In my design i have used spartan2,xc2s200 fg256 family of FPGA.After routing is complete,i generate the IBIS model for FPGA.But the model doesn't show all the pins of FPGA,though all the pins are locked. Can anybody suggest me,why this is happening?IS anybody from XILINX core team suggest me solution?