I'm working on a V2Pro design that needs to have a small portion operate at over 400 MHz. As I've looked into the timing, I've noticed that similar routing between slices seems to have different timing delays. For example:
Location Delay type Delay(ns)
------------------------------------------------- SLICE_X34Y1.YQ Tcko 0.374
SLICE_X34Y3.BY net (fanout=1) 0.614 SLICE_X34Y3.CLK Tdick 0.202
------------------------------------------------- Total 1.190ns
**************************************************Location Delay type Delay(ns)
------------------------------------------------- SLICE_X66Y42.YQ Tcko 0.374
SLICE_X66Y44.BY net (fanout=1) 0.407 SLICE_X66Y44.CLK Tdick 0.202
------------------------------------------------- Total 0.983ns
Note that both circuites route from a YQ output, jump two slices, then go to a BY input. Yet, the net delays vary by 200 psec.
Ideally, I'd pack the 2 flip-flops in one slice, but in my design they are clocked by opposite clock edges as I convert a DDR signal from the negedge into the posedge domain.
Can anyone explain the difference in interconnect delay? Does Xilinx publish anything that really explains how to get the shortest routing delay?
Thanks!
John Providenza