I understand that Xilinx will be doing a Floating Point Unit that uses the APU interface. I haven't been able to find out how big a foot print it will have within a given FPGA. I also don't know what the cost will be. Has anyone heard anything about this? Thanks
Hi Laguna_b1,
You are correct - Xilinx will indeed be releasing a Floating-Point Unit for the PowerPC 405 cores in the Virtex4 FX family, using the pipeline-coupled APU bus interface. This was demonstrated at the Embedded Systems Conference in San Francisco in March:
As for price, footprint, availability... you have all the information that's currently available, I'm afraid! I can't offer any further details at this time. If you're interested, drop me a line with details of your application.
Cheers,
-Ben-
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