Xilinx FPGAs in battery-powered scenarios

Ralphie, let's not sink to kindergarten level. We all can multiply current and time. Most of use even understand percentages... The OP did not give any specific values, and the thread has deteriorated into generalities.

Notealso that there are different degrees of powerdown. As l> Aust> > Rick,

between current, time and energy.

and of course it matters.

thought we were

What's up with you? No one's gotten offensive until you made the kindergarten comment. From his post it is clear that he is missing something about the problem being stated. I didn't get offensive about this. I just explained with plenty of detail to clear up the point of confusion.

Of course it is possible that you don't want to clarify the point of confusion, I can't say. But I don't get what you mean when you say "there are different degrees of powerdown". Power down to me has always meant *no* power. Is there some other power state that is called "powerdown" that I don't know about? How do you mean the term? If you maintain Vcc, why would you need to reconfigure the FPGA?

What is going on here? I am just trying to discuss a technical issue. Don't get your knickers in a knot!

For some ideas on what "power down" might consist of, take a look at the power discussions in the Spartan-3L data sheet. While the idea of a low-power FPGA initially piqued my interest, the method of "deep hibernation" (or some similar term) where the configuration is lost but still some power is used seemed to me a bit bizarre but this functionality might be critical in a system that needs other (milliamp) devices operating continuously without the VCCINT==0 FPGA bringing down the system. With the VCCINT==keeperVoltage, the I/Os might now behave nicely without the full-voltage quiescent power of the FPGA.

Outside of the 3L data sheet (and possible application notes or TechXclusive articles thereof) there isn't a great deal of "low power" discussions in the Xilinx literature for modern FPGAs that I'm aware of.

If nothing else, the 3L information can broaden your ideas on possible power-down (or power-saving) scenarios.

- John_H

ralphie,

Perhaps I am missing something?

Rick mentioned "significant" penalty for reconfiguring, and I pointed out that a few hundred mA (at the most) is all we are talking about.

It is up to the engineer to decide if a few hundred mA is significant, given the benefit (don't reconfigure, need a larger part with more leakage, do reconfigure, and you can potentially use a much smaller part, more efficiently).

No one mentioned turning things off, or "sleep" modes as far as I know.

Really very simple, and very straightforward.

If you also bring into the mix just turning everything off, then doing anything at all, other than leaving everything off, that is infititely "significant" (anything more than 0).

Austin

Designers also have the option to lower Vcc, to go into a Hold-Pgm mode, and so they trade off the energy of doing that, against the energy of full removal, and then reconfig. This shifts the static cost down, so moves the Config power higher up the significance scale.

I've not seen FPGA vendors spec a 'energy optimium' vcc for config.

Also look at other vendors, some offer more choices on power-save modes.

uC designers are fairly used to all this.

-jg

My idea was that eeprom cells would use less power after powerup. I dault the powersurge (if any) is a power consumption problem.

Jim Granville schrieb:

But that one is not built in a 65nm technology, right? Static sv. dynamic power consumption changed a lot with newer technologies.

Kolja Sulimma

Peter Alfke schrieb:

Yes, at least 75% of us. But the remaining half cannot even spill simple words correctly.

Kolja Sulimma

What endless repetition? It seems very clear at this point that Austin is stuck in the rut of comparing only current and not realizing that the device can be completely powered down in a real application. I still have not seen a post by him that acknowledges that. It only makes sense that if you have modes where a device is not used and the static current is significant, you would not keep it powered up. If you keep power on it, then why would you need to reconfigure it when you are ready to use it again?

No, this may not be what the OP was talking about, but this is what I have been talking about. This is what I do on some of my designs. Many chips are capable of very low currents when powered but not used, including some brands of FPGAs. But when I need low power and parts like a Xilinx FPGA are not in use, I remove power to eliminate the high static power consumption. If I can't afford the time or the energy required to reconfigure (short duration of run time relative to the configuration time) then I have to use one of the brands of FPGA that are instant on. This even excludes some of the Flash FPGAs because they are dual mode with the Flash being copied into RAM.

It is very clear that Austin is reading from a different page. My post was an attempt to get him to understand what was being discussed. I still don't see what you are complaining about. Power is what is stored in the battery and is related to the product of current and time. I can draw very large currents for a short time and not deplete the battery significantly. I can also draw very low currents and make a significant dent in the battery if the time is long. Austin simply did not address this in his posts.

I don't appreciate your kindergarten comment. You continue to make it by saying "also". Please refrain from personal comments like this. It is not appropriate in this newsgroup.

Peter Alfke wrote:

the

Thank you, rickman, for that lecture. Kindergarten seems to be a dirty word... But people in glass houses should not throw stones. (Remember your ongoing personal attacks on Austin?) I just got impatient with these trivial arguments running in a circle, making generalized comments, when everything depends on the specific circumstances. We have better things to do than that... Peter Alfke

Why is the process relevent to design selection ? The FPGA vendor chooses what tradeoffs to make, and then release a spec. I design using that spec. If their trade-off's miss the customer's target needs, they miss the sale.

Of course; and some vendors are more focused on power than others. Actels latest Igloo variant makes for interesting reading

I presume their values are valid, but was interesting to see the PolarPro way down the bottom, and also that Coolrunner II is so poor, nearly as bad as MAX II (for their test conditions).

Be interestng to see the SAME test with 98% idle, and 2% run, and even 99.8% idle and 0.2% run.

On the portable-power spin front, I do have to smile at Altera's push on the MAX II - their power off/wakeup suggestions look like Diode-Transistor Logic decades old. Seems they hope customers will ignore PCB/Stocking/Placement costs of all those bits....

-jg

-jg