Xilinx FPGA routing question

Folks,

I have this question for a long time, just could not get an answer.

Assume we have a design consisting of several blocks and some of those blocks are hinhly regular (for example, a datapath). When we do P&R, does the tool take the advantage of this regularity and place those datapath element in series? Or it just does P&R globally without looking at the local regularity?

The reason I am asking this is that we have a design with blocks which are regular inside. But after P&R, the LUT utilization increases dramatically, it seems it uses lots LUT for routing which isn't expected just by looking at the regularity of the blocks.

Thanks.

Reply to
Heliboy
Loading thread data ...

You may try to do some manual floor planning then let the router do the rest...

Don't expect the machine to understand everything you know...

Kelvin

Reply to
Kelvin

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.