XILINX FPGA: DCM locked Signal

Hi,

Is the locked signal of DCM, is synchronous / Asynchronous ?

Regards, Muthu

Reply to
Muthu
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Muthu,

It is generated on the rising edge of CLKIN -- synchronous.

Aust> Hi,

Reply to
Austin Lesea

So is possible the situation desscribed below ?

- the DCM is locked on an input clock;

- I stop completly the clock (from outside the FPGA),

- the DLL looses lock, but the LOCKED signal is never updated and remain high

I think I observed something like that. If it is correct, it's a disturbing feature.

Tullio

Reply to
Tullio Grassi

Tullio,

That is what the status bit "CLK_IN_STOPPED" is for.

Aust> So is possible the situation desscribed below ?

Reply to
Austin Lesea

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