Xilinx Floorplanner

What is the best source for learning about the Xilinx floorplanner?

I see stuff in the constraints documentation but the docs are a bit sketchy on the overall strategy of floorplanning.

What's the difference between the post place and the post map floorplanner as shown on the process pane of the ISE 7.1 ?

How do I add registers to allow a bus to transverse across the chip and not have the synth tool pack the registers into an SRL16?

Brad Smallridge aivision dot com

Reply to
Brad Smallridge
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Depends on what you want to learn. The mechanics of the floorplanner tool are described in the users guide, however it is fairly intuitive, so you may find it easier to just start using it (although you might not stumble across all the features that way)

The strategy is more art than science. It is sort of like putting together a puzzle which has many possible solutions. You should start with a block diagram of your design, grouping the pieces together on paper to minimize the lengths of critical interconnect. Then you use that as a guide to placing the pieces. It helps tremendously to do the floorplanning hierarchically rather than attempting it on a flat design, as it is far easier to optimize small pieces and then place them in the larger design than it is to optimize the whole thing at once. Unfortunately, the floorplanner is not all that hierarchical. You can use the hierarchy browser to work on the design more or less hierarchically. Basically you want critical connections to be short, preferably in the same row/column for source and destination. Carry chains are typically the long pole in the tent, so you want flip-flops outputting to carry chain logic located in close proximity to the carry chain. Best bet is to play with it with some small designs to get a feel for how it works and to start learning some placement strategies.

Post map floorplanner only shows the stuff you manually placed. The rest of the design is not yet placed, so that information is not shown. The post PAR floorplanner brings up an additional pane that shows the actual placement of all of the elements in the design. You can use the post PAR floorplanner to tweak an automatic placement in order to improve the timing.

It has to be done in your RTL of course. The easiest way to prevent SRL16 inference is to put a reset on the flip-flops. You can also do it by putting syn_keeps on the signal between each flip-flop, or a syn_preserve on the flip-flops, or with a synthesis directive. I've had varying success with the synthesis directive, often finding it doesn't work right. I've also had difficulties from synthesis version to synthesis tool version of different behaviors for syn_keep and syn_preserve in certain cases (the most notable is inputs to carry chains...synplicity currently infers an additional lut if you put a syn keep on an instantiated carry chain bit input).

Hope that helps.

Reply to
Ray Andraka

That's what I was expecting.

It seemed that what I was looking at was completely flattened, part of the mapping process? The only thing that was grouped was the carry chains for some of the counters in the design. Everything else was in top. Should I be adding constraints to my vhdl code instead of using the floorplanner?

I still don't know what RTL is.

That's clever.

Very much, thanks.

Brad Smallridge aivision dot com

Reply to
Brad Smallridge

The design is hierarchical, ie. different VHDL components for each submodule, yes? If so then the edif netlist should be hierarchical. Make sure the synthesizer you are using isn't set to flatten the design, and check in PAR to verify the properties are set to flatten.

Register Transfer Level design. It is basically the device independent HDL source code. My usage above is I guess improper. I should have said "It has to be done in your source of course".

Whatever. It works.

Reply to
Ray Andraka

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