I'm having some hard time to understand what's wrong with this Xilinx floating-point core included in the last IP update for LogicCORE.
My design requires me to acquire data from an ADC and then, after some processing to do a division between a couple floating point numbers every
200ns.The performances of the core aren't big enough to use just one, so I implemented a core which feeds several dividers(made with the Xilinx core) and then I reserialize it all.
The design works fine till I pass numbers with a period down to 260ns, going for lower periods the results get weird: the mantissa is correct, the exponent instead is always fixed to 00111111, whatever it's supposed to be instead.
If anybody can offer some insight or even suggest a way of debugging, it would be much appreciated because at the moment I don't have any idea of what could be wrong.
Thanks in advace,
kl31n