Xilinx FIFOs round 2 - BUG-BUG in MPMC2

it seems that Xilinx has real problems getting even simple FIFOs to work after having problems with Virtex4 coregen FIFOs I have now succesfully wasted - about 2 weeks, because another Xilinx FIFO bug! :(

because of REALLY low performance of the EDK multichannel DDR2 core, OPB_MCH_DDR2 - bandwidth 50MByte/s when bursting, and below 20MByte/s for random access I have tried to use MPMC2 IP Core

The FPGA test design failed memory test, actually it stalled on first read to the memory.

After long troubleshooting with the FPGA board, DSO and finally full system EDK simulations the problem is found - namly the fifo used in MPMC2 read data path fails to de-assert empty flag in all cases where the data width is 32 and not 64 I have now tried all combinations of parameters, and all fail succesfully (of course the fifo file header lists 32 bit as supported width). This has naturally an effect that first OPB read to the DDR2 memory never completes.

Antti (not very happy about the time wasted with another Xilinx Bug)

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Antti
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Hi Antti, What ver of MPMC2 are you using? They fix OPB related bug in the october release.

Antti wrote:

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leevv

"leevv" schrieb im Newsbeitrag news: snipped-for-privacy@j44g2000cwa.googlegroups.com...

I am using the latest version, I will check later what version but the read datapath fifo is as broken as it can be - in all cases when its configured as 32 bit wide, its just isnt working that has the effect that OPB PIM fails

Antti

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Antti Lukats

leevv schrieb:

release 10202006 october 20th?

BUG : PRESENT, OPB just doesnt work

Antti

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Antti

We had the problem with 2 ppc trying to share opb bus through the internal PLB to OPB bridge. On the august mpmc2 release, PPCs just hang when had simultaneous access to the same OPB peripheral.

We used workaround with standard external PLB2OPB bridge. THen we test new version (october) and found that this problem gone. But we didn't switch our design to the new core and still using august ver with workaround (don't want to introduce new bugs)

I found that mpmc2 design team is more or less cooperative when you report the bugs. Lately they reguire to open webcase, but before I just sent them email directly and they did respond quickly.

Reply to
leevv

"leevv" schrieb im Newsbeitrag news: snipped-for-privacy@l12g2000cwl.googlegroups.com...

I wanted to have simplest system, eg the MPMC2 is configured with

1 port, OPB, and is used as main memory to MicroBlaze

this is really simple config, and as per datasheet defenetly allowed config options. but - the OPB PIM just doesnt work, because of the FIFO bug...

Antti

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Antti Lukats

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