it seems that Xilinx has real problems getting even simple FIFOs to work after having problems with Virtex4 coregen FIFOs I have now succesfully wasted - about 2 weeks, because another Xilinx FIFO bug! :(
because of REALLY low performance of the EDK multichannel DDR2 core, OPB_MCH_DDR2 - bandwidth 50MByte/s when bursting, and below 20MByte/s for random access I have tried to use MPMC2 IP Core
The FPGA test design failed memory test, actually it stalled on first read to the memory.
After long troubleshooting with the FPGA board, DSO and finally full system EDK simulations the problem is found - namly the fifo used in MPMC2 read data path fails to de-assert empty flag in all cases where the data width is 32 and not 64 I have now tried all combinations of parameters, and all fail succesfully (of course the fifo file header lists 32 bit as supported width). This has naturally an effect that first OPB read to the DDR2 memory never completes.
Antti (not very happy about the time wasted with another Xilinx Bug)