Xilinx Fifo Generator Direct Instantiation?

Does anybody know if it is possible to directly instantiate a Xilinx Fifo Generator asynchronous fifo in VHDL? I have a design that requires the use of them, and I think it would be easier to not to have to keep track of different coregen cores as opposed to just having it written into the VHDL. I've seen other xilinx cores that allow this (dds compiler, for instance) but the fifo generator user guide doesn't say anything about it.

Thanks.