Xilinx- Extract a pin layout

Hi- I am in the midst of bringing a Xilinx design to the lab. It is in a larger BGA package and is becoming hard to probe. In order to assist in the lab- I am trying to print out a huge plot that would show the balls and their associated signal with them. I am hoping there is an easy way to do this. We are using ISE 6.2 on a Solaris box.

Tx, WP

Reply to
wpiman
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Have you looked at Chipscope?

Jim snipped-for-privacy@yahoo.com (remove capital letters)

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Reply to
Jim Wu

You should be able to create such a plot with the PACE tool that comes with ISE. Probing the balls will be tough, though. There is a 'probe' feature in FPGA Editor that allows you to add a probes to nets without rerunning PAR. Then if you have a header connected to some unused pins, you can route nets to this header and probe them that way. As the other respondent said, ChipScope is also good for monitoring internal signals.

-Kevin

Reply to
Kevin Neilson

Chipscope will be something we use after we verify clocks/reset and what not. Right now I just want to print up a big sheet so the techs can do some simple probing. I played with pace but didn't get anywhere.

Reply to
wpiman

Open up your design in PACE. The default view is the "Architecture View" which shows the die. If you click on the "Package View" tab on the bottom of the screen then you will see a view of the balls. You may select the top or bottom view, the latter of which will be easier for probing. The placed pins will be shown as filled-in circles. Tooltips will show the net connected to each pin. I don't think you can print this on the diagram, but you can print the picture and print the pin list. You can also set the colors of the balls if you want to highlight certain pins.

-Kevin

Reply to
Kevin Neilson

I may be able to help you if you can send me the pinout (ucf). (use my private email below)

Jim snipped-for-privacy@yahoo.com (remove capital letters)

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Reply to
Jim Wu

WP, Oleda tech has the tool that you are looking for.

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Our online tools will read your PAD output or UCF file and generate a HTML based graphical representation of your footprint. Pins with signal assignments are highlighted, plus you can point to a pin and see the signal assignment.

It also lets you highlight groups of pins such as busses or pins with a common IO standard, or all the signals that begin with PCI, etc. You can save a 'live' copy on your computer or print out views of your choosing.

You can contact me through the website, I'd be glad to set you up with a trial license. It will save you a great deal of time!

John

Reply to
pipjockey

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