Xilinx EDK - Unable to initialize BRAM in Simulation

I am getting the following error message while building a simple system consisting of bram, ppc, uart, plb bus, opb bus, plb2opb bridge. I am trying to use hardware simulation to verify my design. Any help or pointers is greatly appreciated.

thanks swamy

Initializing Memory... Checking ELFs associated with PPC405 instance ppc405_0 for overlap...

Analyzing file hello/executable.elf... ERROR:MDT - Elf file hello/executable.elf does not reside completely within BRAM

memory of processor ppc405_0. ERROR:MDT - Uncheck the `Mark for BRAM Initialization` setting on the software application generating this ELF. INFO:MDT - This ELF file should be downloaded using a debugger, a bootloader or an ACE file. make: *** [implementation/download.bit] Error 1 Done.

Reply to
swamy
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Swamy,

Check the size of the software code to make sure that it will fit in the BRAM space you have allocated.

Shal> I am getting the following error message while building a simple

Reply to
Shalin Sheth

Only block ram can be initialized during an fpga download. If you are trying to run from external ram or cache, you have to download manually with a debugger or boot loader (and uncheck Mark BRAM for initialization, to continue implementation).

If you think you are running entirely from block ram, this probably means your linker script is bad (and is linking your program into memory that is not block ram).

Alan Nishioka snipped-for-privacy@accom.com

Reply to
Alan Nishioka

Hello Alan and Shalin

Thank you very much for your suggestions. PPC's reset vector

0xFFFFFFFC was not part of my plb_bram controller's address space. Once I changed the address space the simulation files were generated successfully. But I ran into another problem while simulating my design. The following error messages were generated by Modelsim 5.7G SE PLUS. Any pointers would be helpful.

# ** Error: (vsim-3043) system_init.v(9): Unresolved reference to 'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_00. # Region: /system_conf # ** Error: (vsim-3043) system_init.v(10): Unresolved reference to 'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_01. # Region: /system_conf # ** Error: (vsim-3043) system_init.v(11): Unresolved reference to 'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_02. # Region: /system_conf # ** Error: (vsim-3043) system_init.v(12): Unresolved reference to 'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_03.

sytem_conf module has the defparams to initialise BRAM. I have tried instantiating the top level system module in a testbench as mentioned in one xilinx's support page :

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But I did not have any success.

Thanks Swamy

Reply to
swamy

Where are your block rams instantiated?

I've not been able to get things like this to work with LUT roms unless they were directly in the top-level module. If I put the instantiations in a sub-module, I get the same sort of error where it can't find the component the INIT is supposed to be associated with. This was actually only a synthesis (XST) problem for me, as the non-Xilinx simulator (iverilog) was able to match the defparam's with sub-module instantiated memories.

So right now, I'm passing the index for a lookup table up to the top-level, and passing the result back down... It's ugly, though worth remembering that the whole thing gets squashed flat before synthesis anyway (my guess is the problem is that the names don't get adjusted properly during this flattening).

Chris

Reply to
Chris Stratton

Hello Chris

The BRAMs are instantiated deep within some wrapper files produced by simgen in Xilinx EDK. I fixed the problem in my design by UNCHECKING the Mixed language simulator option in options->project options->HDL and Simulation of the EDK software. Somehow the Modelsim simulator is not able to override VHDL model parameters using defparam. I read on some website that defparam cannot be used to override VHDL generic variables. so defparams may not work for mixed language simulations. Unchecking results in simgen now generating all the files in verilog and defparams of system_conf module can override any parameter in the low level verilog design files.

Also flattening the design removes hierarchial information, so you may have to run XST with the option of maintaining the hierarchy for structural simualtions but I could not figure out how to do that in Xilinx EDK. so for now I am running behavioural simulations.

I hope the above helps.

Swamy

Reply to
swamy

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