Xilinx EDK PCI

Have you installed a PCI driver for the board on the host PC? What Os are you using?

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Joe

Avnet does not make host drivers. Either way it should still show up on = the Device Manager in Windows or lspci in Linux as an undefined device = if the configuration cycles of the PCI core are working correctly. I = tried to find this out with a logic analyzer but no luck. Thanks for you = help though.

Which EDK version do you use ? Could you paste your MHS file ?

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Hi Seb

I used EDK 6.2

Here's the .mhs

PARAMETER VERSION =3D 2.1.0

PORT clk_40mhz =3D clk_40mhz, DIR =3D I, SIGIS =3D CLK PORT pci_TRDY_N =3D pci_TRDY_N, DIR =3D IO PORT pci_CBE =3D pci_CBE, VEC =3D [0:3], DIR =3D IO PORT pci_DEVSEL_N =3D pci_DEVSEL_N, DIR =3D IO PORT pci_FRAME_N =3D pci_FRAME_N, DIR =3D IO PORT pci_AD =3D pci_AD, VEC =3D [0:31], DIR =3D IO PORT pci_SERR_N =3D pci_SERR_N, DIR =3D IO PORT pci_IDSEL =3D pci_IDSEL, DIR =3D I PORT pci_INTR_A =3D pci_INTR_A, DIR =3D O PORT pci_IRDY_N =3D pci_IRDY_N, DIR =3D IO PORT pci_PAR =3D pci_PAR, DIR =3D IO PORT pci_GNT_N =3D pci_GNT_N, DIR =3D I PORT pci_Freeze =3D pci_Freeze, DIR =3D I PORT pci_PCLK =3D pci_PCLK, DIR =3D I PORT pci_STOP_N =3D pci_STOP_N, DIR =3D IO PORT pci_RST_N =3D pci_RST_N, DIR =3D I PORT pci_REQ_N =3D pci_REQ_N, DIR =3D O PORT pci_PERR_N =3D pci_PERR_N, DIR =3D IO PORT RS232_RX =3D RS232_RX, DIR =3D I PORT RS232_TX =3D RS232_TX, DIR =3D O PORT led_pin =3D led_pin, VEC =3D [0:7], DIR =3D IO PORT sw_pin =3D sw_pin, VEC =3D [0:7], DIR =3D IO PORT sys_clk =3D sys_clk, DIR =3D I, SIGIS =3D Clk PORT sys_rst =3D sys_rst, DIR =3D I

BEGIN microblaze PARAMETER INSTANCE =3D mblaze PARAMETER HW_VER =3D 2.00.a BUS_INTERFACE DLMB =3D d_lmb BUS_INTERFACE ILMB =3D i_lmb BUS_INTERFACE DOPB =3D d_opb BUS_INTERFACE IOPB =3D d_opb PORT CLK =3D clk_40mhz PORT INTERRUPT =3D mblaze_int END

BEGIN bram_block PARAMETER INSTANCE =3D bram PARAMETER HW_VER =3D 1.00.a BUS_INTERFACE PORTA =3D data BUS_INTERFACE PORTB =3D inst END

BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE =3D i_bram_cntrl PARAMETER HW_VER =3D 1.00.b PARAMETER C_BASEADDR =3D 0x00000000 PARAMETER C_HIGHADDR =3D 0x00007FFF BUS_INTERFACE SLMB =3D i_lmb BUS_INTERFACE BRAM_PORT =3D data PORT LMB_Clk =3D clk_40mhz END

BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE =3D d_bram_cntrl PARAMETER HW_VER =3D 1.00.b PARAMETER C_BASEADDR =3D 0x00000000 PARAMETER C_HIGHADDR =3D 0x00007FFF BUS_INTERFACE SLMB =3D d_lmb BUS_INTERFACE BRAM_PORT =3D inst PORT LMB_Clk =3D clk_40mhz END

BEGIN opb_pci PARAMETER INSTANCE =3D pci PARAMETER HW_VER =3D 1.00.b PARAMETER C_BASEADDR =3D 0x00009000 PARAMETER C_HIGHADDR =3D 0x00009FFF PARAMETER C_PCIBAR_NUM =3D 2 PARAMETER C_PCIBAR_LEN_0 =3D 15 PARAMETER C_PCIBAR2IPIF_0 =3D 0x00008000 PARAMETER C_PCIBAR_ENDIAN_TRANSLATE_EN_0 =3D 1 PARAMETER C_PCI_PREFETCH_0 =3D 1 PARAMETER C_PCI_SPACETYPE_0 =3D 1 PARAMETER C_IPIFBAR_NUM =3D 1 PARAMETER C_IPIF_HIGHADDR_0 =3D 0x0000FFFF PARAMETER C_IPIFBAR2PCI_0 =3D 0x0 PARAMETER C_IPIFBAR_ENDIAN_TRANSLATE_EN_0 =3D 1 PARAMETER C_IPIF_PREFETCH_0 =3D 1 PARAMETER C_IPIF_SPACETYPE_0 =3D 1 PARAMETER C_NUM_INTERRUPTS =3D 13 PARAMETER C_OPB_CLK_PERIOD_PS =3D 25000 PARAMETER C_CLASS_CODE =3D 0x028000 PARAMETER C_DEVICE_ID =3D 0x9050 PARAMETER C_DMA_HIGHADDR =3D 0x0000A77F PARAMETER C_DMA_CHAN_TYPE =3D 0 PARAMETER C_DMA_LENGTH_WIDTH =3D 15 PARAMETER C_DEV_MIR_ENABLE =3D 1 PARAMETER C_INCLUDE_DEV_ISC =3D 1 PARAMETER C_IPIFBAR_1 =3D 0x0000A600 PARAMETER C_IPIF_HIGHADDR_1 =3D 0x0000A61F PARAMETER C_IPIFBAR2PCI_1 =3D 0x0 PARAMETER C_IPIFBAR_ENDIAN_TRANSLATE_EN_1 =3D 1 PARAMETER C_IPIF_PREFETCH_1 =3D 1 PARAMETER C_IPIF_SPACETYPE_1 =3D 1 PARAMETER C_PCIBAR_1 =3D 0xFFFFFFF8 PARAMETER C_PCIBAR_LEN_1 =3D 4 PARAMETER C_PCIBAR2IPIF_1 =3D 0x0000A600 PARAMETER C_PCIBAR_ENDIAN_TRANSLATE_EN_1 =3D 1 PARAMETER C_PCI_PREFETCH_1 =3D 1 PARAMETER C_PCI_SPACETYPE_1 =3D 1 PARAMETER C_VENDOR_ID =3D 0x10B7 PARAMETER C_INCLUDE_PCI_CONFIG =3D 1 PARAMETER C_REV_ID =3D 0x01 PARAMETER C_MAX_LAT =3D 0x08 PARAMETER C_MIN_GNT =3D 0x03 PARAMETER C_NUM_IDSEL =3D 1 PARAMETER C_DMA_BASEADDR =3D 0x0000A700 PARAMETER C_PCIBAR_0 =3D 0xFFFF0008 PARAMETER C_IPIFBAR_0 =3D 0x00008000 BUS_INTERFACE MSOPB =3D d_opb PORT TRDY_N =3D pci_TRDY_N PORT OPB_Clk =3D clk_40mhz PORT CBE =3D pci_CBE PORT DEVSEL_N =3D pci_DEVSEL_N PORT FRAME_N =3D pci_FRAME_N PORT AD =3D pci_AD PORT SERR_N =3D pci_SERR_N PORT IDSEL =3D pci_IDSEL PORT INTR_A =3D pci_INTR_A PORT IRDY_N =3D pci_IRDY_N PORT PAR =3D pci_PAR PORT GNT_N =3D pci_GNT_N PORT Freeze =3D pci_Freeze PORT PCLK =3D pci_PCLK PORT STOP_N =3D pci_STOP_N PORT RST_N =3D pci_RST_N PORT REQ_N =3D pci_REQ_N PORT PERR_N =3D pci_PERR_N END

BEGIN opb_uartlite PARAMETER INSTANCE =3D uart PARAMETER HW_VER =3D 1.00.b PARAMETER C_BASEADDR =3D 0x0000A000 PARAMETER C_HIGHADDR =3D 0x0000A0FF PARAMETER C_DATA_BITS =3D 8 PARAMETER C_CLK_FREQ =3D 40000000 PARAMETER C_BAUDRATE =3D 9600 PARAMETER C_USE_PARITY =3D 0 PARAMETER C_ODD_PARITY =3D 0 BUS_INTERFACE SOPB =3D d_opb PORT OPB_Clk =3D clk_40mhz PORT RX =3D RS232_RX PORT TX =3D RS232_TX PORT Interrupt =3D net_gnd END

BEGIN opb_jtag_uart PARAMETER INSTANCE =3D jtag_uart PARAMETER HW_VER =3D 1.00.b PARAMETER C_BASEADDR =3D 0x0000A100 PARAMETER C_HIGHADDR =3D 0x0000A1FF BUS_INTERFACE SOPB =3D d_opb PORT Interrupt =3D net_gnd PORT OPB_Clk =3D clk_40mhz END

BEGIN lmb_v10 PARAMETER INSTANCE =3D d_lmb PARAMETER HW_VER =3D 1.00.a PORT SYS_Rst =3D sys_rst PORT LMB_Clk =3D clk_40mhz END

BEGIN lmb_v10 PARAMETER INSTANCE =3D i_lmb PARAMETER HW_VER =3D 1.00.a PORT SYS_Rst =3D sys_rst PORT LMB_Clk =3D clk_40mhz END

BEGIN opb_v20 PARAMETER INSTANCE =3D d_opb PARAMETER HW_VER =3D 1.10.b PARAMETER C_BASEADDR =3D 0xFF020000 PARAMETER C_HIGHADDR =3D 0xFF0201FF PARAMETER C_PROC_INTRFCE =3D 1 PORT SYS_Rst =3D sys_rst PORT OPB_Clk =3D clk_40mhz END

BEGIN opb_gpio PARAMETER INSTANCE =3D led PARAMETER HW_VER =3D 2.00.a PARAMETER C_BASEADDR =3D 0x0000A200 PARAMETER C_HIGHADDR =3D 0x0000A2FF PARAMETER C_GPIO_WIDTH =3D 8 BUS_INTERFACE SOPB =3D d_opb PORT OPB_Clk =3D clk_40mhz PORT GPIO_IO =3D led_pin END

BEGIN opb_gpio PARAMETER INSTANCE =3D sw PARAMETER HW_VER =3D 2.00.a PARAMETER C_BASEADDR =3D 0x0000A300 PARAMETER C_HIGHADDR =3D 0x0000A3FF PARAMETER C_GPIO_WIDTH =3D 8 BUS_INTERFACE SOPB =3D d_opb PORT GPIO_IO =3D sw_pin PORT OPB_Clk =3D clk_40mhz END

BEGIN opb_intc PARAMETER INSTANCE =3D intc PARAMETER HW_VER =3D 1.00.c PARAMETER C_BASEADDR =3D 0x0000A400 PARAMETER C_HIGHADDR =3D 0x0000A4FF PARAMETER C_IRQ_IS_LEVEL =3D 0 BUS_INTERFACE SOPB =3D d_opb PORT OPB_Clk =3D clk_40mhz PORT Intr =3D bar_int_Intr PORT Irq =3D mblaze_int END

BEGIN opb_interrupt_generator PARAMETER INSTANCE =3D bar_int PARAMETER C_BASEADDR =3D 0x0000A600 PARAMETER C_HIGHADDR =3D 0x0000A60F BUS_INTERFACE SOPB =3D d_opb PORT opb_clk =3D sys_clk PORT Interrupt =3D bar_int_Intr END

BEGIN opb_bram_if_cntlr PARAMETER INSTANCE =3D pk_mem PARAMETER HW_VER =3D 1.00.a PARAMETER C_BASEADDR =3D 0x00008000 PARAMETER C_HIGHADDR =3D 0x0000FFFF END

"seb" wrote in message = news: snipped-for-privacy@webx.sUNCHnE... Which EDK version do you use ?=20 Could you paste your MHS file ?

It looks good. Try to get a PCI design example from Avnet to underline differences

Jackson,

From your other email I noticed that you are using v1_00_b of the opb pci. It was our experience with this version of the core that the PCI target read transactions will hang the PCI bus. This bug was reported Nov 2003. I did a very cursory search of the answers database, and did not see an entry on the topic.

IIRC, config cycles worked okay on the core, so this is not your current problem. I would recomend that you use a more recent revision of the core than v1_00_b. I would assume that this bug is fixed by now, but you might want to ask.

As we could not wait for the bugs to be fixed, we developed a PCI to PLB, and PCI to OPB bridge, with DMA (pci master) support on the PLB side. This core supports bursting on all but the OPB buses at present. We can make this available on a commercial basis. It is wrapped around the Xilinx PCI logicore, which I should note is one of the best documented, most flexible, pieces of IP we have ever used.

Regards, Erik Widding.

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Hi Seb

Avnet doesn't use EDK as far as I know and they only gave us the bitmap = of a PCIX implementation to show that the card works. I will ask them = again about whether they have done EDK implementation since we bought = the board.

Hi Erik

Thanks so much for your input and offer. I am working for a research group at Cal Poly and we have very limited funds. It is a learning experience for us to be able use PCI with our intelligent NIC. However, due to our license agreement with Xilinx, we cannot get any technical support to help us pin point what is wrong with our PCI/OPB core implementation. I'd also like to try implementing the OPB/PCI wrapper to the Xilinx Logicore to get a better understanding of the core. I'd like to know if you're willing to share your OPB/PCI interface wrapper implementation experience.

Thanks for your help Jackson

FYI - our project is on the web at

bridge

parameters

for

any

board

Jackson,

Support for the Universities is provided by:

And not through the regular Xilinx hotline system.

Michigan State University is tasked with being the "University Hotline" for our hundreds of thousands of students world wide. This allows the commercial hotline to provide the best possible solutions to our 'paying customers', and also allows students to work directly with their peers who have been trained by Xilinx to answer their questions.

I hope no one is confused enough (by your email domain)to think that Xilinx has a license that prevents the support of a product!

Aust> Hi Erik

sorry for the possible confusion. my messages on this forum does not reflect my current employer's opinion. However, I do admit that the quality of support on XUP is very poor. But then again, we get what we pay for.

thanks for clearing things up Austin

Jackson Pang

group

for

license

pin

to

better

your

assignments

Board.

Jackson,

Poor support on XUP from MSU? Really? I would like to know of your experience. Perhaps your work is too advanced for their knowledge base?

You may email me directly at austin ___ @ ___ xilinx ___ . ____ com (remove puncuation).

I am sure there are other universities that would like to provide what MSU does (for the benefits they gain from us), so letting us know how well our partners perform is beneficial.

If you are working with EDK, and the PPC, and the various busses, you may be doing work that is well advanced ahead of what the XUP is able to provide right now. This is useful for us to know.

By donating millions of dollars to education, we do not serve ourselves by then ignoring the support (so we do not).

We also can not allow the XUP patrons to use the commercial support as that would adversely impact business.

A delicate balance.

Aust> sorry for the possible confusion. my messages on this forum does not reflect

It has been brought to my attention that the above paragraph appears to be an offer to redistribute the Xilinx PCI Logicore. It was my intention to offer our wrapper sans the Xilinx core. I appologize for any confusion this has caused.

Regards, Erik Widding.