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Xilinx DFS woes

Hello,

I have a oscillator with 16 MHz connected to a gclk pin of a Spartan

3E. Inside the FPGA , I use the 16 MHz clock and a clock generated by multiplying the 16 MHz with 8 with a DFS.

The code is someting like

module bla (..., input clk, ...); wire clk8; clkmult clk_m8 ( .CLKIN_IN(clk), .CLKFX_OUT(clk8) ); always @ (posedge clk) begin (do a lot) end always @ (posedge clk8) begin (do a lot with a lot of registers) end endmodule

clkmult is a generated by the clock wizard for external input, no reset and no feedback.

I banged my head against the code, but always PAR tells: WARNING:Route:455 - CLK Net:ale_IBUFG may have excessive skew because 2 CLK pins and 1 NON_CLK pins failed to route using a CLK template.

Any hints on what I do wrong?

Thanks

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply to
Uwe Bonnes
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Hi Uwe, Did you connect the clock to an IOB? If you connect it to things that aren't dedicated clk pins you'll see warnings like that. You can use the FPGA editor tool to see where the clock net connects. HTH, Syms.

Reply to
Symon

clk connects to Pin 82 (IO_L11P_2/D2/GCLK2) on a XC3S500E-208. Config mode is Serial Master, so the dual mode function D2 should not be used. As shown, I normally don't instantiate Clock Buffer, but while fiddling around I also tried that with no avail.

For a test I connected the DFS input to some other (non-clock) FPGA input, and clk was routed with a global net.

I use webpack 9.1 on suse 10.2. I already tried to run fpga_editor, as your answer in another thread found with Google groups suggests. Starting fpga_editor however makes the disk spin and the CPU work for a while, a window flash up and disappear immediate. I tried also the DISPLAY =:0 trick, but to no avail.

Thanks

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply to
Uwe Bonnes

Hi Uwe, So the clk comes out of the FPGA on Pin 82, right? If that's the case, you should probably use the IOB's DDR registers to get the clock out. If you wire the data input of the rising edge DDR FF to '1' and the input to the falling edge FF to '0', then connect the clock to the clk input of both, the clock will appear on the output and your clock net will only connect to clk pins. HTH, Syms.

Reply to
Symon

clk is a input. An oscillator is connected on pin 82.

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply to
Uwe Bonnes

Hi Uwe, OK, in that case my advice is useless!

So, does your cct look like?

IOB ---> clk ----> bufg -|--> DCM ---> bufg ----> clk8 | |--> FFs, etc.

Cheers, Syms.

Reply to
Symon

As my code example showed, I like to write code without instantiating manufacturer specific code. So I let it to ISE to invoke the BUFGs. Obviously it doesn the right thing when no DCM is connected to the GCLK input pin, and it does the right thing for the output of the DCM. However with the DCM, I need to explicitly instantiate the BUFG between the GCLK input and the DCM to use the output of the BUFG to drive the clock nets.

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply to
Uwe Bonnes

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