There's been a little side discussion about the Xilinx IOB cell DDR output registers. The common idea of a DDR output register is A) the use of two registers clocked off different phases of the same clock with a mux controlled by the clock so the register just updated goes out.
It was my recollection from dicussions here that B) the DDR output register didn't have a physical mux but was effectively a two-clock register.
Is it A or B ?
There are 2 clock inputs for the two registers in the IOB schematic representation. What will happen when 100 MHz is applied on one clock and a
50 MHz clock with the rising edge coincident with the 100 MHz falling edge applied to the other clock? This is not true DDR but the edges are aligned to DDR transition locations.Will we see confused operation where the mux is controlled by clock1 or clock2 and the different rates produce undefined behavior or will the values be updated with the respective rising edges independent of the logic level of either clock?
I've been considering using two BUFGMUX gated clocks to produce outputs from two sections of my design through the DDR register based on the dual-clock register. If there is a real mux, this operation would be confused without additional DDR implementation understanding. Is there a definitive word on these registers?
As an aside, I've seen Syplify will now infer DDR registers if coded properly but their coding template includes the clock-controlled mux rather than a dual-edge register. Conceptually the muxed register is reasonable but a silicon implementation would either need propagation control for the mux to switch to the just-updated register after the clock-to-out time or would need a transition control such that a low/high/high sequence wouldn't glitch low between the highs or vice-versa. I put together logic a decade ago to bridge this gap in a discreete ECL solution that WAS glitching before applying the bridge logic.