Xilinx DDR output registers

There's been a little side discussion about the Xilinx IOB cell DDR output registers. The common idea of a DDR output register is A) the use of two registers clocked off different phases of the same clock with a mux controlled by the clock so the register just updated goes out.

It was my recollection from dicussions here that B) the DDR output register didn't have a physical mux but was effectively a two-clock register.

Is it A or B ?

There are 2 clock inputs for the two registers in the IOB schematic representation. What will happen when 100 MHz is applied on one clock and a

50 MHz clock with the rising edge coincident with the 100 MHz falling edge applied to the other clock? This is not true DDR but the edges are aligned to DDR transition locations.

Will we see confused operation where the mux is controlled by clock1 or clock2 and the different rates produce undefined behavior or will the values be updated with the respective rising edges independent of the logic level of either clock?

I've been considering using two BUFGMUX gated clocks to produce outputs from two sections of my design through the DDR register based on the dual-clock register. If there is a real mux, this operation would be confused without additional DDR implementation understanding. Is there a definitive word on these registers?

As an aside, I've seen Syplify will now infer DDR registers if coded properly but their coding template includes the clock-controlled mux rather than a dual-edge register. Conceptually the muxed register is reasonable but a silicon implementation would either need propagation control for the mux to switch to the just-updated register after the clock-to-out time or would need a transition control such that a low/high/high sequence wouldn't glitch low between the highs or vice-versa. I put together logic a decade ago to bridge this gap in a discreete ECL solution that WAS glitching before applying the bridge logic.

Reply to
John_H
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The Xilinx design actually uses an XOR gate rather than a mux on the outputs of two independent flip-flops. The scenario you suggest with two clocks should work as long as there is a minimum spacing met between the edge to one flip-flop and the edge to the other.

This has to do with the D in the flip-flops which uses the Q output of the opposite flip-flop. This only works if the opposite flip-flop is not changing at the same time.

The D to each flip-fl> There's been a little side discussion about the Xilinx IOB cell DDR output

Reply to
Gabor

Draw a picture. The rising edge of the 50MHz clock will only be coincident with every other 100MHz falling edge.

Reply to
Duane Clark

and a

edge

aligned

Sure, but my point is that *every* 50 MHz transition is coincident with *a*

100 MHz falling edge, not that every 50 MHz transition is coincident with EVERY 100 MHz falling edge. Draw a picture. Yikes.

If you don't have ABABABABABABAB register interlacing, what happens? In the example I apparantly failed to illustrate - or draw a picture - I'm looking at an example sequence such as ABA-ABA-ABA-ABA where A is the 100 MHz clock and B is the phase shifted 50 MHz clock and the "-" represents no activity because the 50 MHz edge is falling.

Reply to
John_H

or C, something with an XOR (nope)

or D, something else:

The Virtex-II DDR flops are described in patent 6777980 and is available at:

formatting link

or

formatting link

The architecture is more a pair of transparent latches, and a mux-ish structure that does not really have an equivalent in normal logic.

Philip

Philip Freidin Fliptronics

Reply to
Philip Freidin

You're a good man, Philip. This information is what I needed. If only the patent wasn't so hard to comprehend!

It'll take some time to understand what *would* happen with two (nearly) independent clocks where the only restriction is that the rising edges aren't "close" but the information is there.

Thanks aga> >There's been a little side discussion about the Xilinx IOB cell DDR

output

register

Reply to
John_H

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