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XILINX DCMs and synthesis results

I have been wondering about how to use DCMs in a design lets say im doing some dsp filter design and I want my embedded multipliers to run as fast as possible. I synthesize my design using ISE or some other tool and my design synthesizes with a clock rate of say 75 mhz. Now lets say I add my DCMs and asychronous FIFO's to this design around the embedded multipliers. The thing that worries me is that i still have some delays in my clock signal, as well as in the data signals in my design. When I use the DCM, how do i know that the clock wont switch faster than the device can actually register? When designing something like this how do you know what is a safe multiplication factor so that all signals will behave as expected?

thanks

--
Geoffrey Wall
Masters Student in Electrical/Computer Engineering
Florida State University, FAMU/FSU College of Engineering
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Reply to
geoffrey wall
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Geoff,

I would set the clock constrints for the fastest clock that is to be used out of the DCM.

Aust> I have been wondering about how to use DCMs in a design

Reply to
Austin Lesea

Geoffrey,

There is no really a number, at least I never got an accurate one, for safety of adding the new block to a design., but...

If the FIFO you add has nothing to do with the multipliers, and FPGA usage is, say, less than 80%, I would not worry. But if you do.... well, it's always a good idea to maximize the frequency for using less multipliers for DSP filter design, where DCM could be highly useful, but here comes the trade-off... The rest of the logic should be pipelined enough to undertake the timing constraints.

Always check out the timing report. 75 MHz is pretty nice & easy frequency nowadays...

Hope this helps.

Vladislav

Reply to
Vladislav Muravin

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