OK, the DCM input clock goes away, and I understand the LOCKED signal is not valid. After the input clock comes back, can you rely on the LOCKED signal to indicate that a DCM reset pulse is needed?
And ditto that question for the STATUS(2) signal when you are using the CLKFX output?
I'm trying to avoid creating an extra independent clock (with some little oscillator) that would be used to clock a state machine to generate the DCM reset pulse when STATUS(1) indicates loss of input clock. So I thought to use the input clock itself for the state machine, and test the LOCKED signal to decide about reset. After all, there's no point in resetting the DCM until after its input clock has returned.
I hoped the Xilinx website might have an example circuit to handle DCM reset, but I couldn't find anything.
Barry Brown