Xilinx DCM for frequency synthesis -- newbie question

I'm trying to use a DCM on a Spartan 3E to synthesize a frequency of 8 MHz but see only a constant 2 volts on the CLKFX output. The google hits on this did not help.

It must be a simple mistake; any ideas what I'm doing wrong? The "****" indicate the lines from the prototype that I've changed.

thanks Bob Smith

================================================================================== module clocks(clkin, clkout1, clkout2);

input clkin; // Digilent Spartan 3e starter kit 50 MHz clock output clkout1; // Wanna be 8 MHz output clkout2; // 50 MHz/32 for comparison

reg [7:0] count;

always @(posedge clkin) begin count

Reply to
Bob Smith
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==================================================================================

1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5

or 16.0

**************
************

two feature

***********

VARIABLE

*********

SYSTEM_SYNCHRONOUS or

frequency synthesis

TRUE/FALSE

I know this sounds like a simple answer, but have you checked your input clock? That was an issue I just had recently. My external oscillator was not generating its 100MHz signal.

-- Mike

Reply to
morphiend

Mike Thanks for the suggestion. Yeah, the divide by 32 was a way to prove that the clock is there. The code (now snipped) builds and seems to run fine but there's no output on CLKFX.

thanks Bob

Reply to
Bob Smith

Have you checked the locked output? if it's not locked, FX would not output anything iirc, as opposed to clk0 which does regardless of lock.

-P@

Reply to
PatC

your DCM is missing reset, if I am not wrong. I dont see any reset on your top level port list. You are getting clkout2, because it is not depending on reset.

Please check.

Regards, JK

Reply to
JK

Thanks for the suggestion. I added a reset from a switch on the board. A reset does not seem to make any difference.

PatC wrote: > Have you checked the locked output? if it's not locked, FX would not > output anything iirc, as opposed to clk0 which does regardless of lock.

Thanks for the suggestion. I tied an LED on the board to the locked status output. The locked status never goes high (perhaps as you suspected). Any ideas why it won't lock?

JK and PatC, thanks both.

Bob Smith

Reply to
Bob Smith

See the line .CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X

*********

The DLL needs clock feedback to lock (and work). So try setting this to 1X.

Reply to
mng

Michael, Thanks for the suggestion. Changing the feedback to 1X did not make a difference although it builds fine. I could have sworn that using

1X in an earlier attempt gave me an error saying that frequency synthesis needed NONE. The Spartan 3 Users Guide (pg 70) says kind of the same thing.

thanks Bob Smith

Reply to
Bob Smith

Since your code sample is snipped, I don't see the BUFG connecting clk0 to clkfb. If you are using clock feedback 1x, this is how it should be connected. Without this feedback, it won't lock.

-P@

Reply to
PatC

When using the DCM for frequency synthesis only you are correct in saying that you don't need to feedback a signal and setting CLK_FEEDBACK to NONE is the right thing to do. I've succesfully used this configuration myself. Strange that the output is at 2V, is this the IO voltage for that bank? If you haven't already done so, i suggest you try and simulate the design, as this may give some clue as to what is going on. Without a RST input you also need to be careful that the clock is running and stable before configuration. Any change in the input clock requires RST to be asserted. I'm also not sure that the LOCKED pin should go high, since the datasheet states that this is asserted when CLKIN and CLKFB are in phase, which of course will never happen in this configuration.

Cheers Rob

Reply to
Rob

Hmm, duty cycle correction is on, which requires the DLL. Turning it off should make feedback unnecessary.

Reply to
mng

Thanks Pat, Michael, Rob.

The clkin line is given a BUFG. Haven't tried the simulation but that is next. Turning off duty cycle correction did not make a difference. The latest Verilog is attached.

thanks Bob Smith

module clocks(clkin, reset, clkout1, clkout2, locked);

input clkin; // Digilent Spartan 3e starter kit 50 MHz clock input reset; // Reset input output clkout1; // Wanna be 8 MHz output clkout2; // 50 MHz/32 for comparison output locked; // DLL lock status

reg [7:0] count;

always @(posedge clkin) begin count

Reply to
Bob Smith

I used the ISE tool "Architecture Wizard" to generate the equivalent DCM block below. You may want to try it out to see if it works any better.

====================================================== module DCM_Verilog(CLKIN_IN, RST_IN, CLKDV_OUT, CLKFX_OUT, CLKIN_IBUFG_OUT, CLK0_OUT, LOCKED_OUT);

input CLKIN_IN; input RST_IN; output CLKDV_OUT; output CLKFX_OUT; output CLKIN_IBUFG_OUT; output CLK0_OUT; output LOCKED_OUT;

wire CLKDV_BUF; wire CLKFB_IN; wire CLKFX_BUF; wire CLKIN_IBUFG; wire CLK0_BUF; wire GND_BIT;

assign GND_BIT = 0; assign CLKIN_IBUFG_OUT = CLKIN_IBUFG; assign CLK0_OUT = CLKFB_IN; BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF), .O(CLKDV_OUT)); BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF), .O(CLKFX_OUT)); IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN), .O(CLKIN_IBUFG)); BUFG CLK0_BUFG_INST (.I(CLK0_BUF), .O(CLKFB_IN)); DCM_SP DCM_SP_INST (.CLKFB(CLKFB_IN), .CLKIN(CLKIN_IBUFG), .DSSEN(GND_BIT), .PSCLK(GND_BIT), .PSEN(GND_BIT), .PSINCDEC(GND_BIT), .RST(RST_IN), .CLKDV(CLKDV_BUF), .CLKFX(CLKFX_BUF), .CLKFX180(), .CLK0(CLK0_BUF), .CLK2X(), .CLK2X180(), .CLK90(), .CLK180(), .CLK270(), .LOCKED(LOCKED_OUT), .PSDONE(), .STATUS()); defparam DCM_SP_INST.CLK_FEEDBACK = "1X"; defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0; defparam DCM_SP_INST.CLKFX_DIVIDE = 25; defparam DCM_SP_INST.CLKFX_MULTIPLY = 4; defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; defparam DCM_SP_INST.CLKIN_PERIOD = 20.000; defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE"; defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW"; defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW"; defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "FALSE"; defparam DCM_SP_INST.FACTORY_JF = 16'hC080; defparam DCM_SP_INST.PHASE_SHIFT = 0; defparam DCM_SP_INST.STARTUP_WAIT = "FALSE"; endmodule ======================================================

Reply to
John LeVieux

Thanks, John. The Spartan User's Guide talked about the clock wizard but it is a Windows only feature so I've not been able to try it since I sit at a Linux box. My original post was wrong in that I said I have a Spartan 3E. In fact it is just a Spartan 3. I removed the "_SP" references to change from a

3E to a 3 and it compiled correctly. Sad to say there's still no output except on the divide-by-32 counter output.

I'll try simulating the DCM this weekend when I can spend more time on it.

Thanks very much for posting the wizard output.

Bob Smith

(snip)

Reply to
Bob Smith

I also checked the DCM output with Xilinx Coregen wizard. Except that Coregen infers DCM_SP for dcm, than DCM, the simulation outputs of Bob code and coregen inferred code are same. 8 MHz output is coming on clkout2.

Bob, this may be the problem with Hardware. Please check whether ther is any short on the board of clock output pin with VCC.

Regards, JK

Reply to
JK

Bob! I am using the Spartan 3E, and have been dealing with the exact same situation as you have, for the entire weekend!!! Just now after reading all of your attempts and thoughts I got it working! I was careful to notice when you would follow up on all of the suggestions, and that helped me to speed up by skipping the ones that you already tried for me!! :)

BUT !!! There was one suggestion that I thought sounded good, but you replied to 3 suggestions at once, and kind of missed the RST comment. I put a reset delay counter at the beginning of the code to be sure the "clkin" frequency has already been adjusted and stablized. My board changes the default from 12Mhz to 24Mhz from an EEPROM sometime near startup, so I added about a 1 second delay keeping RST high during that period, then dropping once the initial delay was complete and finally I got my LED to flash on the CLKFX output clock counter !!!!

Sorry for the excitement, but when I saw that little LED flashing and double checked the code, it felt really satisfying if you know what I mean! Hope the same solution works for you !!

Sam

Reply to
samonestopva

You need to monitor LOCKED output. When the DCM loses lock, reset should be asserted for a period equal to or greater than 3 valid CLKIN cycles.

Regards, JK

Reply to
JK

This was the best comment with precise and accurate statements from the documentation. A lot of other people give suggestions too but some didn't give from the documentation, just they make it up. Good job Rob!!!

Ciao for now, Sam

Reply to
samonestopva

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