Xilinx DCM

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Hi all,

i am facing a problem with Xilinx DCM in DFS (not in DLL mode, in which
you need to provide a feedback clock for phase alignmen). So my DCM is
working in without feedback (internal as well as external) mode.

 I am trying to generate a 32Mhz clock from a 16Mhz input clock. Most
of the time it works fine but sometimes after giving a reset to FPGA or
reprogramming the FPGA the DCM is not able to multiply the clock to
give a 32Mhz clock and gives the same input 16Mhz clock as the output.

But according to Xilinx DCM datasheet, in DFS mode we should be able to
multiply or divide clocks with frequency > 1 Mhz.

So if anyone has faced any such problem or if there is any synthesis
attribute which I need to set etc then please guide me.

Thanks in advance
Debashish


Re: Xilinx DCM
Debashish,

The DFS part of the DCM is more than happy to work with inputs down to 1
MHz as long as the multiplier results in an output of > 24 MHz.

Do you intentionally use the reset pin?  Or are you using the internal
reset on startup?  If you are not resetting intentionally some time
after configuration is complete and the input clock is stable, it may be
that the input glitches right as the part is trying to lock.

Try a delayed reset to the DCM.

The only way the DCM will not lock is if the input clock is glitching
while it is trying to lock.  Once it has tried, and failed, it will just
output the 1X clock (the input) as you described until it is reset.
LOCK remains low throughout.

If the output is correct for a while, and LOCK does go high, and then
the DFS fails, that is a different issue which is caused by excessive
input jitter.

Austin

snipped-for-privacy@gmail.com wrote:

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Re: Xilinx DCM
We occasionally have problems with the DCMs not locking. I just made a  
simple "DCM watchdog". It is a state machine starting at system reset. It  
first resets the DCM, then waits for the DCM to lock (as long as specified  
in the data sheet). If the DCM doesn't lock, the state machine starts over  
(resetting the DCM again).

-  Elling


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Re: Xilinx DCM
I discovered that I had to provide feedback from CLK0 to CLKFB to get CLKFX
from the DFS.. I dont know if this is a requirement, but at least it gave me
the CLKFB I needed.

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Re: Xilinx DCM
Morten,

CLKFX is only required if the CLK0, 90, 180, 270, CLK2X, or CLKDV output
is also being used (besides the CLKFX output).

I suspect you are using something more than just CLKFX, which has
triggered the software to use the DLL which requires CLKFB.

Note that CLKFB min frequency limit is above 24 MHz...

Austin

Morten Leikvoll wrote:

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