Xilinx Corgen & Synplicity... Anyone? Help?

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Hey all,

  Thanx in advance for any help.  I've got a few FIFO cores that I
created in Xilinx Core Generator.  I instantiated them in my top level
VHDL, and added the syplicity blackbox declarations after the component
declarations, as specified in the various Xilinx/Synplicity documents:

-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of serial_fifo : component is true;

   I added the top level vhdl, and the Xilinx generated EDIF netlists
to my synplicity project... when I run it I get:

warning ID MT246 : Blackbox output_fifo_fifo_generator_v2_3_xst_1 is
missing a user supplied timing model.

  Now, from everything I read in the various PRF documents, the purpose
of adding the EDIF files to the synplicity project is to generate said
timing?  No?  Anyone know why synplicity is complaining here?   Thanx.


Re: Xilinx Corgen & Synplicity... Anyone? Help?
Hi,

Synplify gives you a warning, and not an error. It just tells you that
it is not able to extract the timing behavior of the IP that you
declared as black box. Here, it doesn't read the netlists. This is not
really a problem if your design is not timing critical.

Normally, Synplify_pro can read back the different edf and edn
netlists. You have to add an
  add_file -edif "edif_file_name"
to your *.prj project file and delete the attributes you added in your
VHDL code.

However, when generating a FIFO, coregen generates edn files, but also
an *.ngc file. This file should be converted into an *.ndf file (using:
ngc2edif  *.ngc) and then added to the Synplify_pro project if you want
it to extract the timing behavior of the IP.

Remember that Synplify then optimizes the logic which is around the IP
(in the modules written in VHDL/Verilog), but it won't re-optimize the
netlist itself unless you ask it to do so with the syn_macro attribute.

One last thing: why are you using coregen to generate FIFOs ? There are
many VHDL/Verilog generic FIFO/RAM/ROM models available over the
internet that you could use much more easily ! Make a search over the
posts in this group, you'll have some examples.

Regards,

Arnaud

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Re: Xilinx Corgen & Synplicity... Anyone? Help?
Arnaud,

My only concern with recommending any generic FIFO IP is that you get
what you pay for:  a FIFO is one element that I have seen done wrong
over and over and....

If you use coregen, then you do not have to worry.

Austin

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