Hey all,
Thanx in advance for any help. I've got a few FIFO cores that I created in Xilinx Core Generator. I instantiated them in my top level VHDL, and added the syplicity blackbox declarations after the component declarations, as specified in the various Xilinx/Synplicity documents:
-- Synplicity black box declaration attribute syn_black_box : boolean; attribute syn_black_box of serial_fifo : component is true;
I added the top level vhdl, and the Xilinx generated EDIF netlists to my synplicity project... when I run it I get:
warning ID MT246 : Blackbox output_fifo_fifo_generator_v2_3_xst_1 is missing a user supplied timing model.
Now, from everything I read in the various PRF documents, the purpose of adding the EDIF files to the synplicity project is to generate said timing? No? Anyone know why synplicity is complaining here? Thanx.