Xilinx CoreGen fifo - ngdbuild error

Hi everybody,

since one day I am fighting with a Xilinx CoreGen IP. I am using Mentor Graphics Precision 2006a.101 and Xilinx ISE 9.1. I have a fifo IP generated the Xilinx CORE Generator. In my design, I make an instance of the fifo and can simulate it. For precision, I added two lines to the compilation script:

add_input_file fifo18w16d.v add_input_file -exclude fifo18w16d.edn

Both files were generated by the Xilinx CORE Generator. After compilation and synthesis, I call ngdbuild and get the following error message:

Checking timing specifications ... Checking expanded design ... ERROR:NgdBuild:604 - logical block 'inst_fifo/BU2' with type 'fifo18w16d_fifo_generator_v2_3_xst_1' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'fifo18w16d_fifo_generator_v2_3_xst_1' is not supported in target 'virtex2'.

Partition Implementation Status

-------------------------------

No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary: Number of errors: 1 Number of warnings: 0

One or more errors were found during NGDBUILD. No NGD file will be written.

Writing NGDBUILD log file "Xilinx_CoreGen.bld"...

What is wrong? BTW, this procedure works fine for dual ported RAM created with the CORE Generator.

Thank You very much,

Markus Fras

Reply to
Markus Fras
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Is there a third file in the coregen-directory? There might be an .ngc-file called fifo18w16d_fifo_generator_v2_3_xst_1.ngc. If so, you have to add this to your project as well (also with the -exclude option). The .edn is then just a wrapper for the .ngc, and is way smaller.

I've had this problem before. Even if I explicitely tell CoreGen that I want it to create an EDIF-netlist for third-party tools, I always get an .edn and an .ngc, and I need them both. I don't remember this from earlier ISE-versions, but I might just not have tried all different settings.

HTH, Sean

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Reply to
Sean Durkin

Well, Xilinx CoreGen created two additional files:

fifo18w16d_fifo_generator_v2_3_xst_1.ngc fifo18w16d_fifo_generator_v2_3_xst_1_blkmemdp_v6_2_xst.edn

Even if I include both of the, I still get the same error message.

The solution is to add the output directory of CoreGen to ngdbuild with the switch `-sd'. Then you need only to include the *.v file in the synthesis.

I.e. in the synthesis script only add the line

`add_input_file fifo18w16d.v'

and to the ngdbuild command, add the switch

`-sd '

Cheers,

Markus Fras

Reply to
Markus Fras

Well, this sets the macro search path for the entire project, and ngdbuild just takes whatever it needs from there. Works fine if all your cores are in the same directory, but if they're scattered over several folders, the only way is to add them all to the project.

If you don't set the macro search path explicitely, ngdbuild assumes the implementation directory as source directory for all cores. In this case, Precision has to copy the corresponding files there, which it should do if you add them to the project with the "-exclude"-option, that's what that's for.

Don't know why that doesn't work for you, but I've never had any problems there, as long as I included all the files CoreGen produces.

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Reply to
Sean Durkin

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