Hi everybody,
since one day I am fighting with a Xilinx CoreGen IP. I am using Mentor Graphics Precision 2006a.101 and Xilinx ISE 9.1. I have a fifo IP generated the Xilinx CORE Generator. In my design, I make an instance of the fifo and can simulate it. For precision, I added two lines to the compilation script:
add_input_file fifo18w16d.v add_input_file -exclude fifo18w16d.edn
Both files were generated by the Xilinx CORE Generator. After compilation and synthesis, I call ngdbuild and get the following error message:
Checking timing specifications ... Checking expanded design ... ERROR:NgdBuild:604 - logical block 'inst_fifo/BU2' with type 'fifo18w16d_fifo_generator_v2_3_xst_1' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'fifo18w16d_fifo_generator_v2_3_xst_1' is not supported in target 'virtex2'.
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary: Number of errors: 1 Number of warnings: 0
One or more errors were found during NGDBUILD. No NGD file will be written.
Writing NGDBUILD log file "Xilinx_CoreGen.bld"...
What is wrong? BTW, this procedure works fine for dual ported RAM created with the CORE Generator.
Thank You very much,
Markus Fras