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xilinx core generator

Hello,

Im new to Xilinx core generator tool and have a very fundamental question. I want to generate a single port RAM with an enable signal for the READ operation and the WRITE operation.

The write operation works fine. For the read operation, I want to see the output only when a read_enable signal is asserted. I used the "ENA pin" but when asserted I dont see the required output. When I choose the option "Always enabled", it works fine and I see the previous output always. But I want the output only when the read_enable signal is asserted.

Can this be done? Thanks for your help.

--Vandana

Reply to
Vandana
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If your memory is generated with block RAM, the ENA pin is actually common to read and write for the single port RAM. So writing will update the data outputs unless you have specified a RAM with output registers and a separate register enable. Also, the output from the block ram will always update on the cycle after the ENA pin is asserted. If you want asynchronous readout, you need to use distributed memory instead.

Regards, Gabor

Reply to
Gabor

Thanks, I realised the ENA pin is common to Read/Write and Reset.

Reply to
Vandana

If you use the block RAMs as read-before-write, you will not see the update until read-with-enable (or multiple, sequential write enables.)

For this, you do not need to use CoreGen; you can just instantiate the library directly, and apply the appropriate attributes. See the appropriate Xilinx library document.

JTW

Reply to
jtw

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