Hello,
Im new to Xilinx core generator tool and have a very fundamental question. I want to generate a single port RAM with an enable signal for the READ operation and the WRITE operation.
The write operation works fine. For the read operation, I want to see the output only when a read_enable signal is asserted. I used the "ENA pin" but when asserted I dont see the required output. When I choose the option "Always enabled", it works fine and I see the previous output always. But I want the output only when the read_enable signal is asserted.
Can this be done? Thanks for your help.
--Vandana