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Xilinx constraint question- DC input

Hi- I need to add something to my UCF file and I am not entirely sure how to do it.

We have a chip that is going to operate in one of two modes. We will have a pin which will be tied high on one side- and low on the other.

The problem is is that this signal fans out throughout the whole device- but that timing analyzer thinks that this is an input it has to run timing analysis on.

What we would like to do is tell the timing analyzer that the pin "mode" will not change- and that it should not consider this in its timing calculations.

Thanks, WP

Reply to
wpiman
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From the Constraints Guide:

TIG (Timing IGnore) is a basic timing constraint and a synthesis constraint. It causes paths that fan forward from the point of application (of TIG) to be treated as if they do not exist (for the purposes of the timing model) during implementation.

The basic UCF syntax is: NET ?net_name? TIG; PIN ?ff_inst.RST? TIG=TS_1; INST ?instance_name? TIG=TS_2; TIG=TSidentifier1,..., TSidentifiern

Regards, Allan

Reply to
Allan Herriman

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