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Xilinx: Connecting an on-chip memory-like component to Microblaze

Hi, I'm new to Xilinx devices and tools so please bear with my ignorance.

I have an on-chip component that interfaces off chip devices (ADC's, etc.) to the Microblaze processor. The interface is precisely a port of a dual-port BRAM.

1) Initially, I thought it would be easiest to simply map the various signals into GPIO of the Microblaze (speed at this point is not important, getting something running is). But the GPIO seem to only want to talk to the device pins. Anyone know how to insert a component between GPIO and device pins?

2) I've also tried to use a memory style interface using either the OPB-to-BRAM controller or the LMB-to-BRAM controller. However, no "Wizard" or component instaniator will fill in all the parameters correctly, and if I try to modify the files (*.mpd or wrapper *.vhd) either they get rewritten over with the original incorrect values or won't compile. Any suggestions on working this interface will be appreciated.

Thanks for any help.

Tom

Reply to
Tom J
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Oops, I realized I omitted that it's a Virtex-4, in particular the Avnet LX25 Evaluation board.

Tom

Reply to
Tom J

Try creating an EDK design that has opb_bram. This will instantiate a bram block with one port of the BRAM connected to the opb_bram controller. Connect the other port of the BRAM to your peripheral.

/Siva

Reply to
Siva Velusamy

This may be of interest:

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take the above file through the import IP wizard, tell it you have a OPB slave interface, and map the IOs to OPB signals as appropriate. I was able to make this compile and route painlessly, though I haven't tested it out by actually running it.

Reply to
Jeff Cunningham

OK, I've tried this. (I had to select the opb_bram while creating a new project, the option isn't available in the IP Catalog of an open project.) Now I'm back to the same problem I had originally. How do I connect these signals, the unattached BRAM port, to my project without the compiler rewriting the original configurations over my edits?

Tom

Reply to
Tom J

Could you post the relevant MHS/MPD sections and the error messages?

I'm guessing the bram_block section should look like this:

BEGIN bram_block PARAMETER INSTANCE = opb_bram_if_cntlr_1_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = opb_bram_if_cntlr_1_port BUS_INTERFACE PORTB = custom_pcore_bram_port END

and your custom_pcore should have an entry like so:

BUS_INTERFACE PORTA = custom_pcore_bram_port

If its still complicated, please file a hotline case.

/Siva

Reply to
Siva Velusamy

Up to now, I've only been modifying the compiler produced MPD files. I assume from your post that I should be generating files of my own as well/instead. Is there a reference for these files? When to use them, what goes in them, their format, etc.?

Tom

Reply to
Tom J

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Thanks for the code, Jeff. I inserted it and it did indeed compile. But as you say it's not been debugged and I'd have to modify for my purposes. I'll keep it on hold for now.

Tom

Reply to
Tom J

Pardon me for replying to my own post, but as FYI for everyone I've found the following Xilinx reference manual that details the usage and format of the MHS, MPD, PAO, BBD, MSS, MDD, MLD and XBD files:

Platform Specification Format Reference Manual

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Reply to
Tom J

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