Xilinx : Clock Swallowing

Our current design uses clock swallowing to obtain lower frequency clocks. I'd like to implement this clocking behaviour (while still maintaining the phase relationahip between the clocks) inside a VIRTEX4 but don't know if this is possible. For example:

I input a 44MHz clock.

I generate a 22MHz clock with 25/75 duty cycle by gating every second 44MHz pulse.

How can I maintain the phase relationship between the new 22Mhz clock and the origianl 44MHz clock ??

All the clock divide options of the DCM's and PMCD's will have 50/50 duty cycle outputs. Is there no method of obtaining a divided phase aligned non 50/50 duty cycle clock?

regards, Luke darnell

Reply to
Luke Darnell
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As the saying goes there is more than one way to skin the cat. The DCM's will allow phase shift and multiplication. One way, and not the only way, is multiply your origional 44 MHz. If you then generate clock enables from a state machine / counter you can choose effectively different widths and phases that you want.

As a suggestion multiply the 44Mhz by 2 to 88MHz and that will give 4 phases of 22MHz to turn on, or off, as you like. The clock enable can be synched to the input using a sample of the 44MHz clock. If you want real clock signals you can use the state machine / counter outputs, or derived functions, but be careful of routing timing skews. However this technique does work well if it is external clocks you are generating and you use the I/O cell flip-flop to generate the final output.

John Adair Enterpoint Ltd. - Home of MINI-CAN. Low Cost Spartan-3 PCI Development Boards.

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Reply to
John Adair

I'd like to implement this clocking behaviour (while still maintaining the phase relationahip between the clocks) inside a VIRTEX4 but don't know if this is possible. For example:

44MHz pulse.

the origianl 44MHz clock ??

cycle outputs. Is there no method of obtaining a divided phase aligned non

50/50 duty cycle clock?

Hi Luke, So, whatever you do, don't gate the clock in the fabric. It's _bad_. Search this group to find out why. I'd suggest, for stuff inside the FPGA, you should use your 44 MHz clock with an enable every other clock. If you want to send a 22MHz clock out of the FPGA, use this enable with the double data rate registers (search for DDR) in the IOBs to get what you want. If your input clock has a bad duty cycle a DCM could clean this up before the DDR. Have fun swallowing, Syms.

Reply to
Symon

like to implement this clocking behaviour (while still maintaining the phase relationahip between the clocks) inside a VIRTEX4 but don't know if this is possible. For example:

pulse.

origianl 44MHz clock ??

cycle outputs. Is there no method of obtaining a divided phase aligned non 50/50 duty cycle clock?

how about two bufgce's, both with the 44MHz as input, one always on the other on every other cycle?

-Lasse

Reply to
Lasse Langwadt Christensen

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