Our current design uses clock swallowing to obtain lower frequency clocks. I'd like to implement this clocking behaviour (while still maintaining the phase relationahip between the clocks) inside a VIRTEX4 but don't know if this is possible. For example:
I input a 44MHz clock.
I generate a 22MHz clock with 25/75 duty cycle by gating every second 44MHz pulse.
How can I maintain the phase relationship between the new 22Mhz clock and the origianl 44MHz clock ??
All the clock divide options of the DCM's and PMCD's will have 50/50 duty cycle outputs. Is there no method of obtaining a divided phase aligned non 50/50 duty cycle clock?
regards, Luke darnell